| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_crat.c | 59 .cache_line_size = 64,
69 .cache_line_size = 64,
79 .cache_line_size = 64,
95 .cache_line_size = 64,
105 .cache_line_size = 64,
115 .cache_line_size = 64,
145 .cache_line_size = 64,
155 .cache_line_size = 64,
165 .cache_line_size = 64,
175 .cache_line_size = 64,
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| H A D | kfd_crat.h | 168 uint16_t cache_line_size; member
304 uint32_t cache_line_size; member
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| /linux/arch/mips/mm/ |
| H A D | page.c | 87 static int cache_line_size; variable
88 #define cache_line_mask() (cache_line_size - 1)
136 cache_line_size = cpu_dcache_line_size(); in set_prefetch_parameters()
205 cache_line_size = cpu_scache_line_size(); in set_prefetch_parameters()
207 cache_line_size = cpu_dcache_line_size(); in set_prefetch_parameters()
214 max(cache_line_size >> 1, in set_prefetch_parameters()
217 max(cache_line_size >> 1, in set_prefetch_parameters()
238 } else if (cache_line_size == (half_clear_loop_size << 1)) { in build_clear_pref()
299 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) in build_clear_page()
300 * cache_line_size : 0; in build_clear_page()
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| /linux/tools/perf/util/ |
| H A D | cacheline.c | 6 #define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) macro
10 static void cache_line_size(int *cacheline_sizep) in cache_line_size() function
22 cache_line_size(&size); in cacheline_size()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| H A D | alloc.c | 136 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()
165 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()
177 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()
218 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
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| /linux/arch/parisc/include/asm/ |
| H A D | cache.h | 31 #define cache_line_size() dcache_stride macro
32 #define dma_get_cache_alignment cache_line_size
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| /linux/arch/arm64/include/asm/ |
| H A D | cache.h | 86 int cache_line_size(void);
88 #define dma_get_cache_alignment cache_line_size
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| /linux/arch/arm64/kernel/ |
| H A D | cacheinfo.c | 15 int cache_line_size(void) in cache_line_size() function
22 EXPORT_SYMBOL_GPL(cache_line_size);
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| /linux/tools/testing/selftests/vDSO/ |
| H A D | vdso_test_getrandom.c | 66 size_t state_size_aligned, cache_line_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) ?: 1; in vgetrandom_get_state() local
69 …ate_size_aligned = (vgrnd.params.size_of_opaque_state + cache_line_size - 1) & (~(cache_line_size … in vgetrandom_get_state()
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| /linux/drivers/infiniband/sw/rxe/ |
| H A D | rxe_queue.c | 77 if (elem_size < cache_line_size()) in rxe_queue_init()
78 elem_size = cache_line_size(); in rxe_queue_init()
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| /linux/drivers/scsi/cxlflash/ |
| H A D | common.h | 173 } __aligned(cache_line_size());
228 } __aligned(cache_line_size());
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| H A D | sislite.h | 480 char carea[cache_line_size()]; /* 128B each */
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| /linux/arch/um/include/asm/ |
| H A D | processor-generic.h | 84 #define cache_line_size() (boot_cpu_data.cache_alignment) macro
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| /linux/arch/arc/include/asm/ |
| H A D | cache.h | 51 #define cache_line_size() SMP_CACHE_BYTES macro
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| /linux/Documentation/PCI/endpoint/function/binding/ |
| H A D | pci-test.rst | 18 cache_line_size don't care
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| H A D | pci-ntb.rst | 18 cache_line_size don't care
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | mmu_rb.c | 51 free_ptr = kzalloc(sizeof(*h) + cache_line_size() - 1, GFP_KERNEL); in hfi1_mmu_rb_register()
55 h = PTR_ALIGN(free_ptr, cache_line_size()); in hfi1_mmu_rb_register()
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| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-endpoint-cfs.rst | 68 ... cache_line_size
132 | cache_line_size
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| /linux/include/linux/ |
| H A D | cache.h | 111 #define cache_line_size() L1_CACHE_BYTES macro
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| /linux/drivers/pci/endpoint/ |
| H A D | pci-ep-cfs.c | 437 PCI_EPF_HEADER_R(cache_line_size)
438 PCI_EPF_HEADER_W_u8(cache_line_size)
455 CONFIGFS_ATTR(pci_epf_, cache_line_size);
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| /linux/tools/virtio/ringtest/ |
| H A D | ptr_ring.c | 14 #define cache_line_size() SMP_CACHE_BYTES macro
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| /linux/drivers/pci/ |
| H A D | pci-bridge-emul.h | 14 u8 cache_line_size; member
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| H A D | pci-acpi.c | 148 u8 cache_line_size; /* Not applicable to PCIe */ member
156 .cache_line_size = 8,
175 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); in program_hpx_type0()
210 hpx0->cache_line_size = fields[2].integer.value; in decode_type0_hpx_record()
754 hpx0.cache_line_size = fields[0].integer.value; in acpi_run_hpp()
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| /linux/arch/powerpc/kernel/ |
| H A D | eeh_pe.c | 54 alloc_size = ALIGN(alloc_size, cache_line_size()); in eeh_pe_alloc()
69 cache_line_size()); in eeh_pe_alloc()
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| /linux/block/ |
| H A D | blk-flush.c | 489 rq_sz = round_up(rq_sz + cmd_size, cache_line_size()); in blk_alloc_flush_queue()
|