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Searched refs:c15 (Results 1 – 25 of 29) sorted by relevance

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/linux/arch/arm/mm/
H A Dproc-v7.S199 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
200 mrc p15, 0, r5, c15, c0, 0 @ Power register
208 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
210 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
211 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
213 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
238 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
239 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
240 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
241 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
[all …]
H A Dproc-feroceon.S74 mcr p15, 1, r0, c15, c9, 0 @ clean L2
266 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
267 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
345 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
346 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
377 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
378 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
435 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
[all …]
H A Dproc-sa110.S38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
H A Dproc-sa1100.S42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
H A Dcache-v6.S74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
187 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
268 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
H A Dproc-v6.S164 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
216 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
H A Dproc-xsc3.S426 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
444 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
467 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
H A Dproc-xscale.S516 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
532 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
549 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
H A Dproc-mohawk.S354 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
372 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
H A Dproc-arm925.S441 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
452 mcr p15, 7, r0, c15, c0, 0
H A Dproc-arm1026.S415 mcr p15, 7, r0, c15, c0, 0
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
/linux/arch/arm/include/asm/
H A Darm_pmuv3.h29 #define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7)
87 #define PMEVTYPER24 __ACCESS_CP15(c14, 0, c15, 0)
88 #define PMEVTYPER25 __ACCESS_CP15(c14, 0, c15, 1)
89 #define PMEVTYPER26 __ACCESS_CP15(c14, 0, c15, 2)
90 #define PMEVTYPER27 __ACCESS_CP15(c14, 0, c15, 3)
91 #define PMEVTYPER28 __ACCESS_CP15(c14, 0, c15, 4)
92 #define PMEVTYPER29 __ACCESS_CP15(c14, 0, c15, 5)
93 #define PMEVTYPER30 __ACCESS_CP15(c14, 0, c15, 6)
/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S49 mrc p15, 0, r2, c15, c0, 0
51 mcr p15, 0, r2, c15, c0, 0
116 mrc p15, 0, r2, c15, c0, 0
118 mcr p15, 0, r2, c15, c0, 0
/linux/arch/arm/include/asm/hardware/
H A Dcp14.h72 #define RCP14_DBGBVR15() MRC14(0, c0, c15, 4)
88 #define RCP14_DBGBCR15() MRC14(0, c0, c15, 5)
104 #define RCP14_DBGWVR15() MRC14(0, c0, c15, 6)
120 #define RCP14_DBGWCR15() MRC14(0, c0, c15, 7)
137 #define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1)
177 #define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4)
193 #define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5)
209 #define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6)
225 #define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7)
241 #define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1)
[all …]
/linux/arch/arm/kernel/
H A Diwmmxt.S72 mrc p15, 0, r2, c15, c1, 0
78 mcr p15, 0, r2, c15, c1, 0
205 mrc p15, 0, r4, c15, c1, 0
207 mcr p15, 0, r4, c15, c1, 0
217 mcr p15, 0, r4, c15, c1, 0
312 mrc p15, 0, r1, c15, c1, 0
325 mcr p15, 0, r1, c15, c1, 0
/linux/arch/arm/mach-tegra/
H A Dreset-handler.S160 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
163 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
173 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
176 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
/linux/arch/arm/mach-imx/
H A Dheadsmp.S21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
/linux/tools/perf/arch/s390/include/
H A Ddwarf-regs-table.h45 REG_DWARFNUM_NAME(c15, 47),
/linux/arch/arm/mach-mvebu/
H A Dpmsu_ll.S14 mrc p15, 4, r1, c15, c0 @ get SCU base address
/linux/arch/s390/kernel/
H A Dreipl.S28 stctg %c0,%c15,__LC_CREGS_SAVE_AREA(%r13)
/linux/arch/arm/mach-sa1100/
H A Dsleep.S34 mcr p15, 0, r1, c15, c2, 2
/linux/arch/s390/boot/
H A Dhead.S256 lctlg %c0,%c15,0(%r13) # load control registers
304 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8)
/linux/arch/arm/include/debug/
H A Dbrcmstb.S68 mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c368 c9, c10, c11, c12, c13, c14, c15) \ argument
374 VC4_PPF_FILTER_WORD(c15, c15, 0)}

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