/linux/arch/arm/include/asm/ |
H A D | arm_pmuv3.h | 23 #define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0) 24 #define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1) 25 #define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) 26 #define PMCEID2 __ACCESS_CP15(c9, 0, c14, 4) 27 #define PMCEID3 __ACCESS_CP15(c9, 0, c14, 5) 28 #define PMMIR __ACCESS_CP15(c9, 0, c14, 6) 29 #define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7) 31 #define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0) 32 #define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1) 33 #define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2) [all …]
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/linux/arch/arm/include/asm/hardware/ |
H A D | cp14.h | 71 #define RCP14_DBGBVR14() MRC14(0, c0, c14, 4) 87 #define RCP14_DBGBCR14() MRC14(0, c0, c14, 5) 103 #define RCP14_DBGWVR14() MRC14(0, c0, c14, 6) 119 #define RCP14_DBGWCR14() MRC14(0, c0, c14, 7) 136 #define RCP14_DBGBXVR14() MRC14(0, c1, c14, 1) 147 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6) 176 #define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4) 192 #define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5) 208 #define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6) 224 #define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7) [all …]
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/linux/arch/arm/mm/ |
H A D | cache-fa.S | 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 132 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 155 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 179 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 182 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry 216 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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H A D | cache-v6.S | 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 185 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 220 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line 266 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
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H A D | proc-mohawk.S | 117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 145 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 206 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 272 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 323 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
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H A D | proc-arm925.S | 173 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 207 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 210 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 270 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 405 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
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H A D | proc-arm926.S | 137 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 170 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 233 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 304 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 368 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
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H A D | proc-arm1022.S | 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 248 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 320 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 380 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
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H A D | proc-arm1026.S | 145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 315 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 374 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
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H A D | proc-arm922.S | 136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 223 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 288 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 354 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
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H A D | proc-arm1020e.S | 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 249 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 321 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 384 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
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H A D | proc-feroceon.S | 156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 185 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 188 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start 314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top 362 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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H A D | proc-arm946.S | 113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 216 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 288 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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H A D | proc-arm1020.S | 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 181 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 254 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 333 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 398 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
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H A D | proc-arm920.S | 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 221 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 286 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 351 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
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H A D | cache-v7.S | 166 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way 349 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 376 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 381 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 428 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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H A D | proc-arm940.S | 119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 174 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 245 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
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H A D | proc-xsc3.S | 69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 255 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 317 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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H A D | proc-v6.S | 162 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 214 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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H A D | proc-fa526.S | 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
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/linux/arch/arm/include/debug/ |
H A D | icedcc.S | 48 mrc p14, 0, \rx, c14, c0, 0 61 mrc p14, 0, \rx, c14, c0, 0
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/linux/arch/arm/common/ |
H A D | secure_cntvoff.S | 26 mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
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/linux/arch/arm/include/asm/vdso/ |
H A D | cp15.h | 32 #define CNTVCT __ACCESS_CP15_64(1, c14)
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/linux/tools/perf/arch/s390/include/ |
H A D | dwarf-regs-table.h | 44 REG_DWARFNUM_NAME(c14, 46),
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/linux/arch/arm/boot/compressed/ |
H A D | head.S | 1230 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 1245 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 1253 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D 1267 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 1277 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA 1290 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
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