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/linux/arch/arm/include/asm/hardware/
H A Dcp14.h45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
/linux/drivers/gpu/drm/tidss/
H A Dtidss_scale_coefs.c19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
49 .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, },
55 .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, },
61 .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, },
67 .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, },
73 .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, },
[all …]
/linux/arch/arm/mm/
H A Dproc-v6.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
118 mcr p15, 0, r1, c13, c0, 1 @ set context ID
148 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
150 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
[all …]
H A Dproc-v7.S35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
38 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
148 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
150 mrc p15, 0, r8, c1, c0, 0 @ Control register
[all …]
H A Dproc-sa1100.S43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
153 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
182 mrc p15, 0, r4, c3, c0, 0 @ domain ID
183 mrc p15, 0, r5, c13, c0, 0 @ PID
184 mrc p15, 0, r6, c1, c0, 0 @ control reg
[all …]
H A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
115 mcr p15, 0, r0, c3, c0
119 mcr p15, 0, r0, c5, c0 @ all read/write access
[all …]
H A Dproc-xsc3.S57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
425 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
427 mrc p15, 0, r6, c13, c0, 0 @ PID
[all …]
H A Dproc-mohawk.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
327 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
353 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
355 mrc p15, 0, r6, c13, c0, 0 @ PID
356 mrc p15, 0, r7, c3, c0, 0 @ domain ID
357 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
H A Dproc-arm926.S52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
93 mrc p15, 0, r1, c1, c0, 0 @ Read control register
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
403 mrc p15, 0, r4, c13, c0, 0 @ PID
[all …]
H A Dproc-xscale.S70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
117 mrc p15, 0, r1, c1, c0, 1
119 mcr p15, 0, r1, c1, c0, 1
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
152 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
160 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
[all …]
H A Dcache-v7.S44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
46 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
101 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
129 mrc p15, 1, r0, c0, c0, 1 @ read clidr
144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
146 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
180 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
H A Dproc-arm940.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
317 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
318 mcr p15, 0, r0, c2, c0, 1
324 mcr p15, 0, r0, c3, c0, 0
[all …]
/linux/arch/arm/include/debug/
H A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
89 mrc p14, 0, \rx, c0, c0, 0
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s514 cxsin $c0
515 cxsout $c0
525 cxsin $c0
526 cenc $c0 $c0
527 cxsout $c0
533 cxsin $c0
534 cdec $c0 $c0
535 cxsout $c0
540 cxsin $c0
541 cxor $c6 $c0
[all …]
/linux/arch/arm/include/asm/
H A Duaccess-asm.h50 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
62 mcr p15, 0, \tmp, c3, c0, 0
76 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
90 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
132 DACR( mrc p15, 0, \tmp0, c3, c0, 0)
134 PAN( mrc p15, 0, \tmp0, c2, c0, 2)
139 mcr p15, 0, \tmp2, c3, c0, 0
145 mcr p15, 0, \tmp2, c3, c0, 0
[all …]
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
189 mrc p15, 0, r0, c1, c0, 0
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
[all …]
H A Domap-headsmp.S46 mrc p15, 0, r4, c0, c0, 5
64 mrc p15, 0, r4, c0, c0, 5
86 mrc p15, 0, r4, c0, c0, 5
103 mrc p15, 0, r4, c0, c0, 5
/linux/lib/crypto/
H A Dpolyval.c74 u128 c0 = (a0 * (u128)b0) ^ (a1 * (u128)b3) ^ in clmul64() local
92 *out_lo = (((u64)c0) & 0x1111111111111111) ^ in clmul64()
96 *out_hi = (((u64)(c0 >> 64)) & 0x1111111111111111) ^ in clmul64()
123 u64 c0 = (a0 * (u64)b0) ^ (a1 * (u64)b3) ^ in clmul32() local
133 return (c0 & 0x1111111111111111) ^ in clmul32()
161 u64 c0, c1, c2, c3, mi0, mi1; in polyval_mul_generic() local
167 clmul64(le64_to_cpu(a->lo), le64_to_cpu(b->lo), &c0, &c1); in polyval_mul_generic()
171 mi0 ^= c0 ^ c2; in polyval_mul_generic()
190 c1 ^= (c0 << 63) ^ (c0 << 62) ^ (c0 << 57); in polyval_mul_generic()
191 c2 ^= c0 ^ (c0 >> 1) ^ (c0 >> 2) ^ (c0 >> 7); in polyval_mul_generic()
/linux/arch/arm/mach-tegra/
H A Dsleep.h70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
H A Dsleep.S40 mrc p15, 0, r2, c1, c0, 0
43 mcrne p15, 0, r2, c1, c0, 0
65 mrc p15, 0, r0, c0, c0, 5
70 mrc p15, 0x1, r0, c9, c0, 2
75 mcrne p15, 0x1, r0, c9, c0, 2
116 mrc p15, 0, r3, c1, c0, 0
120 mcr p15, 0, r3, c1, c0, 0
/linux/tools/testing/selftests/proc/
H A Dproc-uptime-001.c30 uint64_t start, u0, u1, c0, c1; in main() local
38 c0 = clock_boottime(); in main()
48 assert(c1 >= c0); in main()
51 assert(c0 >= u0); in main()
54 c0 = c1; in main()
H A Dproc-uptime-002.c47 uint64_t u0, u1, c0, c1; in main() local
66 c0 = clock_boottime(); in main()
82 assert(c1 >= c0); in main()
85 assert(c0 >= u0); in main()
88 c0 = c1; in main()
/linux/Documentation/admin-guide/media/
H A Ddvb-usb-gp8psk-cardlist.rst16 - 09c0:0200, 09c0:0201
18 - 09c0:0202
20 - 09c0:0203
22 - 09c0:0206
/linux/arch/arm/boot/compressed/
H A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
[all …]

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