Searched refs:buf_mask (Results 1 – 14 of 14) sorted by relevance
58 start = s_start & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()59 end = s_end & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()110 if (chunk->cntl_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()113 if (chunk->ce_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()115 if (chunk->de_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()295 start = e->start_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()296 end = e->end_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()305 e->sw_rptr = (e->sw_cptr + offset) & ring->buf_mask; in amdgpu_ring_mux_get_rptr()428 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()456 chunk->cntl_offset = ring->buf_mask + 1; in amdgpu_ring_mux_start_ib()[all …]
122 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_insert_nop() 123 chunk1 = ring->buf_mask + 1 - occupied; in amdgpu_ring_insert_nop() 347 ring->buf_mask = (ring->ring_size / 4) - 1; in amdgpu_ring_init() 349 0xffffffffffffffff : ring->buf_mask; in amdgpu_ring_init() 627 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read() 628 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read() 629 early[2] = ring->wptr & ring->buf_mask; in amdgpu_debugfs_ring_read() 658 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; in amdgpu_debugfs_virt_ring_read() 659 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; in amdgpu_debugfs_virt_ring_read() 665 avail_dw = ring->buf_mask [all...]
998 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); in gfx_v9_0_kiq_unmap_queues() 5509 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { in gfx_v9_0_ring_emit_ib_compute() 5513 (ring->buf_mask + 1 - offset) << 2); in gfx_v9_0_ring_emit_ib_compute() 5514 payload_size -= (ring->buf_mask + 1 - offset) << 2; in gfx_v9_0_ring_emit_ib_compute() 5516 ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), in gfx_v9_0_ring_emit_ib_compute() 5536 if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { in gfx_v9_0_ring_emit_fence() 5540 (ring->buf_mask + 1 - offset) << 2); in gfx_v9_0_ring_emit_fence() 5541 payload_size -= (ring->buf_mask + 1 - offset) << 2; in gfx_v9_0_ring_emit_fence() 5543 de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), in gfx_v9_0_ring_emit_fence() 5915 ret = ring->wptr & ring->buf_mask; in gfx_v9_0_ring_emit_reg_wait() [all...]
444 ring->buf_mask); in amdgpu_devcoredump_read()
471 for (p = pos + 1; p <= ring->buf_mask; p++) { in amdgpu_cper_ring_get_ent_sz()
638 ret = ring->wptr & ring->buf_mask;
155 ret = ring->wptr & ring->buf_mask; in sdma_v6_0_ring_init_cond_exec()
153 ret = ring->wptr & ring->buf_mask; in sdma_v7_0_ring_init_cond_exec()
147 ret = ring->wptr & ring->buf_mask; in sdma_v7_1_ring_init_cond_exec()
6176 ret = ring->wptr & ring->buf_mask; in gfx_v11_0_ring_emit_gfx_shadow() 6207 offs = ring->wptr & ring->buf_mask; in gfx_v11_0_ring_emit_gfx_shadow()
4648 ret = ring->wptr & ring->buf_mask; in gfx_v12_0_ring_preempt_ib()
83 idx = (send_sq->cur_post + ctrl->num_wqebbs) & send_sq->buf_mask; in mlx5hws_send_engine_post_req_wqe()144 idx = sq->cur_post & sq->buf_mask; in mlx5hws_send_engine_post_end()280 idx = wqe_cnt & send_sq->buf_mask; in hws_send_engine_retry_post_send()287 idx = (wqe_cnt + 1) & send_sq->buf_mask; in hws_send_engine_retry_post_send()621 wqe_cnt = be16_to_cpu(cqe->wqe_counter) & sq->buf_mask; in hws_send_engine_poll_cq()626 cq->poll_wqe = (cq->poll_wqe + priv->num_wqebbs) & sq->buf_mask; in hws_send_engine_poll_cq()630 cq->poll_wqe = (wqe_cnt + priv->num_wqebbs) & sq->buf_mask; in hws_send_engine_poll_cq()716 sq->buf_mask = (queue->num_entries * MAX_WQES_PER_RULE) - 1; in hws_send_ring_alloc_sq()
137 unsigned int buf_mask; member
985 buf_mask