Searched refs:buf_mask (Results 1 – 12 of 12) sorted by relevance
58 start = s_start & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()59 end = s_end & ring->buf_mask; in amdgpu_ring_mux_copy_pkt_from_sw_ring()110 if (chunk->cntl_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()113 if (chunk->ce_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()115 if (chunk->de_offset <= e->ring->buf_mask) in amdgpu_mux_resubmit_chunks()295 start = e->start_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()296 end = e->end_ptr_in_hw_ring & mux->real_ring->buf_mask; in amdgpu_ring_mux_get_rptr()305 e->sw_rptr = (e->sw_cptr + offset) & ring->buf_mask; in amdgpu_ring_mux_get_rptr()428 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()456 chunk->cntl_offset = ring->buf_mask + 1; in amdgpu_ring_mux_start_ib()[all …]
374 uint32_t buf_mask; member490 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); in amdgpu_ring_clear_ring()495 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()505 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()506 chunk1 = ring->buf_mask + 1 - occupied; in amdgpu_ring_write_multiple()540 WARN_ON(offset > ring->buf_mask); in amdgpu_ring_patch_cond_exec()543 cur = (ring->wptr - 1) & ring->buf_mask; in amdgpu_ring_patch_cond_exec()
142 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_insert_nop()143 chunk1 = ring->buf_mask + 1 - occupied; in amdgpu_ring_insert_nop()367 ring->buf_mask = (ring->ring_size / 4) - 1; in amdgpu_ring_init()369 0xffffffffffffffff : ring->buf_mask; in amdgpu_ring_init()592 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read()593 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; in amdgpu_debugfs_ring_read()594 early[2] = ring->wptr & ring->buf_mask; in amdgpu_debugfs_ring_read()
768 unsigned int first_idx = start_wptr & ring->buf_mask; in amdgpu_ring_backup_unprocessed_command()769 unsigned int last_idx = end_wptr & ring->buf_mask; in amdgpu_ring_backup_unprocessed_command()773 for (i = first_idx; i != last_idx; ++i, i &= ring->buf_mask) in amdgpu_ring_backup_unprocessed_command()
303 ring->buf_mask); in amdgpu_devcoredump_read()
155 ret = ring->wptr & ring->buf_mask; in sdma_v6_0_ring_init_cond_exec()
313 ret = ring->wptr & ring->buf_mask; in sdma_v5_0_ring_init_cond_exec()
153 ret = ring->wptr & ring->buf_mask; in sdma_v5_2_ring_init_cond_exec()
4574 ret = ring->wptr & ring->buf_mask; in gfx_v12_0_ring_emit_init_cond_exec()
83 idx = (send_sq->cur_post + ctrl->num_wqebbs) & send_sq->buf_mask; in mlx5hws_send_engine_post_req_wqe()144 idx = sq->cur_post & sq->buf_mask; in mlx5hws_send_engine_post_end()280 idx = wqe_cnt & send_sq->buf_mask; in hws_send_engine_retry_post_send()287 idx = (wqe_cnt + 1) & send_sq->buf_mask; in hws_send_engine_retry_post_send()621 wqe_cnt = be16_to_cpu(cqe->wqe_counter) & sq->buf_mask; in hws_send_engine_poll_cq()626 cq->poll_wqe = (cq->poll_wqe + priv->num_wqebbs) & sq->buf_mask; in hws_send_engine_poll_cq()630 cq->poll_wqe = (wqe_cnt + priv->num_wqebbs) & sq->buf_mask; in hws_send_engine_poll_cq()716 sq->buf_mask = (queue->num_entries * MAX_WQES_PER_RULE) - 1; in hws_send_ring_alloc_sq()
137 unsigned int buf_mask; member
985 buf_mask