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Searched refs:block_sequence (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c653 params = &clk_mgr401->block_sequence[i].params; in dcn401_execute_block_sequence()
655 switch (clk_mgr401->block_sequence[i].func) { in dcn401_execute_block_sequence()
773 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence; in dcn401_build_update_bandwidth_clocks_sequence() local
808 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count; in dcn401_build_update_bandwidth_clocks_sequence()
809 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS; in dcn401_build_update_bandwidth_clocks_sequence()
848 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK; in dcn401_build_update_bandwidth_clocks_sequence()
849block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->cl… in dcn401_build_update_bandwidth_clocks_sequence()
850 block_sequence[num_steps].params.update_hardmin_params.response = NULL; in dcn401_build_update_bandwidth_clocks_sequence()
851 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; in dcn401_build_update_bandwidth_clocks_sequence()
860block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mg… in dcn401_build_update_bandwidth_clocks_sequence()
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H A Ddcn401_clk_mgr.h104 struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE]; member
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c733 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], in hwss_build_fast_sequence()
753 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; in hwss_build_fast_sequence()
754block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_… in hwss_build_fast_sequence()
755 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; in hwss_build_fast_sequence()
759 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
760 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
761 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = in hwss_build_fast_sequence()
763 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; in hwss_build_fast_sequence()
770 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
771 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
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H A Ddc_state.c335 memset(state->block_sequence, 0, sizeof(state->block_sequence)); in dc_state_destruct()
H A Ddc.c4153 context->block_sequence, in commit_planes_for_stream_fast()
4159 context->block_sequence, in commit_planes_for_stream_fast()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h663 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE]; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h981 struct block_sequence { struct
987 struct block_sequence *steps;
1369 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
1375 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],