Searched refs:bclk_ratio (Results 1 – 13 of 13) sorted by relevance
70 u32 bclk_ratio, mclk_ratio; in loongson_i2s_hw_params() local 76 bclk_ratio = DIV_ROUND_CLOSEST(clk_rate, in loongson_i2s_hw_params() 83 val |= (bclk_ratio << 8); in loongson_i2s_hw_params() 89 bclk_ratio = DIV_ROUND_CLOSEST(sysclk, in loongson_i2s_hw_params() 97 val |= (bclk_ratio << 8); in loongson_i2s_hw_params()
50 unsigned int bclk_ratio; member 84 ret = cs40l50_get_clk_config(codec->bclk_ratio * codec->rate, &cfg); in cs40l50_swap_ext_clk() 231 codec->bclk_ratio = ratio; in cs40l50_set_dai_bclk_ratio() 261 codec->bclk_ratio = CS40L50_BCLK_RATIO_DEFAULT; in cs40l50_codec_probe()
41 u32 bclk_ratio; member
161 unsigned int bclk_ratio; member
922 if (cs42l42->bclk_ratio) { in cs42l42_pcm_hw_params() 924 bclk = cs42l42->bclk_ratio * params_rate(params); in cs42l42_pcm_hw_params() 1016 unsigned int bclk_ratio) in cs42l42_set_bclk_ratio() argument 1021 cs42l42->bclk_ratio = bclk_ratio; in cs42l42_set_bclk_ratio()
50 unsigned int bclk_ratio; member913 if (pcm512x->bclk_ratio > 0) { in pcm512x_set_dividers()914 lrclk_div = pcm512x->bclk_ratio; in pcm512x_set_dividers()1452 pcm512x->bclk_ratio = ratio; in pcm512x_set_bclk_ratio()
34 int bclk_ratio;1237 tscs42xx->bclk_ratio = ratio; in tscs42xx_set_dai_bclk_ratio() 33 int bclk_ratio; global() member
537 ucontrol->value.integer.value[0] = i2s->bclk_ratio; in tegra210_i2s_get_bclk_ratio()549 if (value == i2s->bclk_ratio) in tegra210_i2s_put_bclk_ratio()552 i2s->bclk_ratio = value; in tegra210_i2s_put_bclk_ratio()562 i2s->bclk_ratio = ratio; in tegra210_i2s_set_dai_bclk_ratio()576 if (i2s->bclk_ratio) in tegra210_i2s_set_timing_params()577 num_bclk *= i2s->bclk_ratio; in tegra210_i2s_set_timing_params()
172 unsigned int bclk_ratio; member
311 unsigned int bclk_ratio;301 unsigned int bclk_ratio; global() member
261 sai->bclk_ratio = ratio; in fsl_sai_set_dai_bclk_ratio()631 else if (sai->bclk_ratio) in fsl_sai_hw_params()632 slots = sai->bclk_ratio / slot_width; in fsl_sai_hw_params()657 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); in fsl_sai_hw_params()
82 unsigned int srate, unsigned int bclk_ratio)85 clk_set_rate(drvdata->bclk, srate * bclk_ratio);75 acp_clk_enable(struct acp_card_drvdata * drvdata,unsigned int srate,unsigned int bclk_ratio) acp_clk_enable() argument
525 if (dai->bclk_ratio) { in soc_pcm_shared_bclk_rule_rate()531 target_rate = active_bclk_rate / dai->bclk_ratio; in soc_pcm_shared_bclk_rule_rate()