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Searched refs:base_address (Results 1 – 25 of 67) sorted by relevance

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/linux/drivers/char/xilinx_hwicap/
H A Dbuffer_icap.c90 return in_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET); in buffer_icap_get_status()
101 static inline u32 buffer_icap_get_bram(void __iomem *base_address, in buffer_icap_get_bram() argument
104 return in_be32(base_address + (offset << 2)); in buffer_icap_get_bram()
115 static inline bool buffer_icap_busy(void __iomem *base_address) in buffer_icap_busy() argument
117 u32 status = in_be32(base_address + XHI_STATUS_REG_OFFSET); in buffer_icap_busy()
129 static inline void buffer_icap_set_size(void __iomem *base_address, in buffer_icap_set_size() argument
132 out_be32(base_address + XHI_SIZE_REG_OFFSET, data); in buffer_icap_set_size()
143 static inline void buffer_icap_set_offset(void __iomem *base_address, in buffer_icap_set_offset() argument
146 out_be32(base_address + XHI_BRAM_OFFSET_REG_OFFSET, data); in buffer_icap_set_offset()
159 static inline void buffer_icap_set_rnc(void __iomem *base_address, in buffer_icap_set_rnc() argument
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H A Dfifo_icap.c97 out_be32(drvdata->base_address + XHI_WF_OFFSET, data); in fifo_icap_fifo_write()
108 u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); in fifo_icap_fifo_read()
121 out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); in fifo_icap_set_read_size()
130 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK); in fifo_icap_start_config()
140 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK); in fifo_icap_start_readback()
162 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_get_status()
173 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_busy()
186 return in_be32(drvdata->base_address + XHI_WFV_OFFSET); in fifo_icap_write_fifo_vacancy()
198 return in_be32(drvdata->base_address + XHI_RFO_OFFSET); in fifo_icap_read_fifo_occupancy()
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
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/linux/drivers/misc/ibmasm/
H A Dlowlevel.h41 static inline int sp_interrupt_pending(void __iomem *base_address) in sp_interrupt_pending() argument
43 return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in sp_interrupt_pending()
46 static inline int uart_interrupt_pending(void __iomem *base_address) in uart_interrupt_pending() argument
48 return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in uart_interrupt_pending()
51 static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask) in ibmasm_enable_interrupts() argument
53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts()
57 static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask) in ibmasm_disable_interrupts() argument
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts()
63 static inline void enable_sp_interrupts(void __iomem *base_address) in enable_sp_interrupts() argument
65 ibmasm_enable_interrupts(base_address, SP_INTR_MASK); in enable_sp_interrupts()
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H A Dlowlevel.c26 mfa = get_mfa_inbound(sp->base_address); in ibmasm_send_i2o_message()
33 message = get_i2o_message(sp->base_address, mfa); in ibmasm_send_i2o_message()
38 set_mfa_inbound(sp->base_address, mfa); in ibmasm_send_i2o_message()
47 void __iomem *base_address = sp->base_address; in ibmasm_interrupt_handler() local
50 if (!sp_interrupt_pending(base_address)) in ibmasm_interrupt_handler()
60 mfa = get_mfa_outbound(base_address); in ibmasm_interrupt_handler()
62 struct i2o_message *msg = get_i2o_message(base_address, mfa); in ibmasm_interrupt_handler()
67 set_mfa_outbound(base_address, mfa); in ibmasm_interrupt_handler()
H A Dmodule.c96 sp->base_address = pci_ioremap_bar(pdev, 0); in ibmasm_init_one()
97 if (!sp->base_address) { in ibmasm_init_one()
109 enable_sp_interrupts(sp->base_address); in ibmasm_init_one()
136 disable_sp_interrupts(sp->base_address); in ibmasm_init_one()
139 iounmap(sp->base_address); in ibmasm_init_one()
166 disable_sp_interrupts(sp->base_address); in ibmasm_remove_one()
171 iounmap(sp->base_address); in ibmasm_remove_one()
H A Duart.c25 iomem_base = sp->base_address + SCOUT_COM_B_BASE; in ibmasm_register_uart()
48 enable_uart_interrupts(sp->base_address); in ibmasm_register_uart()
56 disable_uart_interrupts(sp->base_address); in ibmasm_unregister_uart()
/linux/drivers/input/serio/
H A Dxilinx_ps2.c68 void __iomem *base_address; /* virt. address of control registers */ member
92 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in xps2_recv()
94 *byte = in_be32(drvdata->base_address + XPS2_RX_DATA_OFFSET); in xps2_recv()
112 intr_sr = in_be32(drvdata->base_address + XPS2_IPISR_OFFSET); in xps2_interrupt()
113 out_be32(drvdata->base_address + XPS2_IPISR_OFFSET, intr_sr); in xps2_interrupt()
163 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in sxps2_write()
167 out_be32(drvdata->base_address + XPS2_TX_DATA_OFFSET, c); in sxps2_write()
192 out_be32(drvdata->base_address + XPS2_GIER_OFFSET, XPS2_GIER_GIE_MASK); in sxps2_open()
193 out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, XPS2_IPIXR_RX_ALL); in sxps2_open()
210 out_be32(drvdata->base_address + XPS2_GIER_OFFSET, 0x00); in sxps2_close()
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/linux/drivers/pinctrl/bcm/
H A Dpinctrl-ns2-mux.c574 void __iomem *base_address; in ns2_pinmux_set() local
609 base_address = pinctrl->base0; in ns2_pinmux_set()
613 base_address = pinctrl->base1; in ns2_pinmux_set()
621 val = readl(base_address + grp->mux.offset); in ns2_pinmux_set()
624 writel(val, (base_address + grp->mux.offset)); in ns2_pinmux_set()
660 void __iomem *base_address; in ns2_pin_set_enable() local
662 base_address = pinctrl->pinconf_base; in ns2_pin_set_enable()
664 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_enable()
670 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_enable()
706 void __iomem *base_address; in ns2_pin_set_slew() local
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H A Dpinctrl-nsp-mux.c391 void __iomem *base_address; in nsp_pinmux_set() local
425 base_address = pinctrl->base0; in nsp_pinmux_set()
429 base_address = pinctrl->base1; in nsp_pinmux_set()
433 base_address = pinctrl->base2; in nsp_pinmux_set()
441 val = readl(base_address); in nsp_pinmux_set()
444 writel(val, base_address); in nsp_pinmux_set()
H A Dpinctrl-nsp-gpio.c96 void __iomem *base_address; in nsp_set_bit() local
99 base_address = chip->io_ctrl; in nsp_set_bit()
101 base_address = chip->base; in nsp_set_bit()
103 val = readl(base_address + reg); in nsp_set_bit()
109 writel(val, base_address + reg); in nsp_set_bit()
/linux/arch/x86/math-emu/
H A Dget_address.c141 unsigned long base_address, limit, address, seg_top; in pm_address() local
163 base_address = seg_get_base(&descriptor); in pm_address()
164 address = base_address + offset; in pm_address()
167 limit += base_address - 1; in pm_address()
168 if (limit < base_address) in pm_address()
175 seg_top = base_address + (1 << 20); in pm_address()
176 if (seg_top < base_address) in pm_address()
184 (address > limit) || (address < base_address) ? 0 : in pm_address()
/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c12 #define print_wrapper_reg(dev, base_address, reg_offset)\ argument
13 internal_print_wrapper_reg(dev, (base_address), #reg_offset,\
15 #define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\ argument
17 val = readl((base_address) + (reg_offset));\
/linux/drivers/iio/adc/
H A Dad7606_par.c125 insw((unsigned long)st->base_address, _buf, 1); in ad7606_par16_read_block()
133 insw((unsigned long)st->base_address, _buf, num); in ad7606_par16_read_block()
159 insb((unsigned long)st->base_address, _buf, 2); in ad7606_par8_read_block()
167 insb((unsigned long)st->base_address, _buf, num * 2); in ad7606_par8_read_block()
H A Dad7606.h148 void __iomem *base_address; member
224 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
/linux/include/acpi/
H A Dactbl2.h761 u64 base_address; /* SMMU base address */ member
797 u64 base_address; /* SMMUv3 base address */ member
856 u64 base_address; member
927 u64 base_address; /* IOMMU control registers */ member
938 u64 base_address; /* IOMMU control registers */ member
1303 u64 base_address; member
1329 u64 base_address; member
1352 u64 base_address; member
1368 u64 base_address; member
1381 u64 base_address; member
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H A Dactbl3.h229 u64 base_address; member
565 u64 base_address; member
580 u64 base_address; member
/linux/drivers/gpu/drm/amd/include/
H A Ddiscovery.h107 uint32_t base_address[]; /* variable number of Addresses */ member
125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ member
143 …DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_ba…
435 uint64_t base_address; member
/linux/drivers/acpi/arm64/
H A Diort.c818 u64 addr = rmr_desc->base_address, size = rmr_desc->length; in iort_rmr_alloc()
836 size = PAGE_ALIGN(size + offset_in_page(rmr_desc->base_address)); in iort_rmr_alloc()
839 rmr_desc->base_address, in iort_rmr_alloc()
840 rmr_desc->base_address + rmr_desc->length - 1, in iort_rmr_alloc()
861 u64 end, start = desc[i].base_address, length = desc[i].length; in iort_rmr_desc_check_overlap()
873 u64 e_start = desc[j].base_address; in iort_rmr_desc_check_overlap()
1520 res[num_res].start = smmu->base_address; in arm_smmu_v3_init_resources()
1521 res[num_res].end = smmu->base_address + in arm_smmu_v3_init_resources()
1592 smmu->base_address, in arm_smmu_v3_set_proximity()
1629 res[num_res].start = smmu->base_address; in arm_smmu_init_resources()
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/linux/arch/x86/include/asm/
H A Diommu.h27 u64 start = rmrr->base_address; in arch_rmrr_sanity_check()
H A Dmsi.h38 base_address : 12; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gmc.c1336 if (ranges[i].base_address >= ranges[i].limit_address) { in amdgpu_gmc_get_nps_memranges()
1340 nps_type, i, ranges[i].base_address, in amdgpu_gmc_get_nps_memranges()
1348 if (max(ranges[j].base_address, in amdgpu_gmc_get_nps_memranges()
1349 ranges[i].base_address) <= in amdgpu_gmc_get_nps_memranges()
1355 ranges[j].base_address, in amdgpu_gmc_get_nps_memranges()
1357 ranges[i].base_address, in amdgpu_gmc_get_nps_memranges()
1365 (ranges[i].base_address - in amdgpu_gmc_get_nps_memranges()
1373 ranges[i].limit_address - ranges[i].base_address + 1; in amdgpu_gmc_get_nps_memranges()
/linux/drivers/mfd/
H A Dls2k-bmc-core.c162 u32 base_address[6]; member
222 pci_write_config_dword(parent, base, ddata->bridge_pci_data.base_address[i]); in ls2k_bmc_restore_bridge_pci_data()
337 pci_read_config_dword(parent, base, &ddata->bridge_pci_data.base_address[i]); in ls2k_bmc_save_pci_data()
/linux/drivers/net/wireless/rsi/
H A Drsi_91x_usb.c504 u32 base_address, in rsi_usb_load_data_master_write() argument
518 status = rsi_usb_write_register_multiple(adapter, base_address, in rsi_usb_load_data_master_write()
525 base_address += block_size; in rsi_usb_load_data_master_write()
533 (adapter, base_address, in rsi_usb_load_data_master_write()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h7138 void *base_address; /**< CPU base address for ring's data */ member
7148 void *base_address; /**< CPU address for the ring's data */ member
7239 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; in dmub_rb_push_front()
7272 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; in dmub_rb_out_push_front()
7302 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_front()
7345 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; in dmub_rb_peek_offset()
7366 …const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rpt… in dmub_rb_out_front()
7420 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); in dmub_rb_flush_pending()
7441 rb->base_address = init_params->base_address; in dmub_rb_init()
7458 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : in dmub_rb_get_return_data()
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/linux/drivers/acpi/
H A Dviot.c163 node->mmio.base_address); in viot_get_iommu()
221 ep->address = node->mmio.base_address; in viot_parse_node()

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