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Searched refs:bankw (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dradeon_object.c611 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
613 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
618 switch (bankw) { in radeon_bo_set_tiling_flags()
H A Devergreen.c1111 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1115 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1119 switch (*bankw) { in evergreen_tiling_fields()
1121 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; in evergreen_tiling_fields()
1122 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; in evergreen_tiling_fields()
1123 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; in evergreen_tiling_fields()
1124 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; in evergreen_tiling_fields()
H A Datombios_crtc.c1146 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1332 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); in dce4_crtc_do_set_base()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c186 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() local
188 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1920 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1922 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1931 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v8_0_crtc_do_set_base()
H A Ddce_v10_0.c1981 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1983 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v10_0_crtc_do_set_base()
H A Ddce_v6_0.c2008 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
2010 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
2019 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v6_0_crtc_do_set_base()