Searched refs:bank_cfg (Results 1 – 3 of 3) sorted by relevance
52 u32 bank_cfg; in gx1_frame_buffer_size() local62 bank_cfg = readl(mc_regs + MC_BANK_CFG); in gx1_frame_buffer_size()65 if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM) in gx1_frame_buffer_size()66 dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8); in gx1_frame_buffer_size()67 bank_cfg >>= 16; /* look at DIMM1 next */ in gx1_frame_buffer_size()
89 int bank_cfg; member189 ret = regmap_write(priv->regmap, LM3697_OUTPUT_CONFIG, priv->bank_cfg); in lm3697_init()267 priv->bank_cfg |= in lm3697_probe_dt()
1058 u64 bank_cfg = (u64)hw_prio << 24; in npc_cn20k_config_mcam_entry() local1105 bank_cfg); in npc_cn20k_config_mcam_entry()1137 bank_cfg); in npc_cn20k_config_mcam_entry()1221 u64 cam0, cam1, bank_cfg, cfg; in npc_cn20k_read_mcam_entry() local1251 bank_cfg = rvu_read64(rvu, blkaddr, in npc_cn20k_read_mcam_entry()1253 *ena = bank_cfg & 0x1; in npc_cn20k_read_mcam_entry()1254 *hw_prio = (bank_cfg & GENMASK_ULL(30, 24)) >> 24; in npc_cn20k_read_mcam_entry()