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Searched refs:bank (Results 1 – 25 of 589) sorted by relevance

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/linux/drivers/gpio/
H A Dgpio-omap.c78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
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H A Dgpio-rockchip.c82 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
85 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
87 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
93 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
96 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
99 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
107 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
111 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
114 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
129 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
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H A Dgpio-brcmstb.c28 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
29 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
30 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
31 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
32 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
33 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
34 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
35 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
36 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
67 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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H A Dgpio-usbio.c43 struct usbio_gpio_bank *bank; in usbio_gpio_get_bank_and_pin() local
46 bank = &gpio->banks[offset / USBIO_GPIOSPERBANK]; in usbio_gpio_get_bank_and_pin()
48 if (~bank->bitmap & BIT(pin)) { in usbio_gpio_get_bank_and_pin()
53 *bank_ret = bank; in usbio_gpio_get_bank_and_pin()
59 struct usbio_gpio_bank *bank; in usbio_gpio_get_direction() local
63 usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin); in usbio_gpio_get_direction()
65 cfg = bank->config[pin] & USBIO_GPIO_PINMOD_MASK; in usbio_gpio_get_direction()
74 struct usbio_gpio_bank *bank; in usbio_gpio_get() local
79 usbio_gpio_get_bank_and_pin(gc, offset, &bank, &pin); in usbio_gpio_get()
97 struct usbio_gpio_bank *bank; in usbio_gpio_set() local
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
82 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
84 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
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H A Dpinctrl-s3c64xx.c217 struct samsung_pin_bank *bank; member
281 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
283 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
291 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
302 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
306 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
309 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
318 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
319 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask()
320 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
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H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
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H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
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H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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H A Dadf_transport_debug.c51 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
52 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
53 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
58 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
60 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
62 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
68 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
111 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
128 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
129 u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev); in adf_bank_start()
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/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c184 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
219 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
222 bank->pin_backup[offset].value = value; in stm32_gpio_backup_value()
225 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
228 bank->pin_backup[offset].mode = mode; in stm32_gpio_backup_mode()
229 bank->pin_backup[offset].alt = alt; in stm32_gpio_backup_mode()
232 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
235 bank->pin_backup[offset].drive = drive; in stm32_gpio_backup_driving()
238 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
241 bank->pin_backup[offset].speed = speed; in stm32_gpio_backup_speed()
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/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
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/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh182 create_bank chip bank
184 test -n `cat $CONFIGFS_DIR/chip/bank/chip_name` || fail "chip_name doesn't work"
190 create_bank chip bank
197 create_bank chip bank
207 create_bank chip bank
215 create_bank chip bank
216 set_num_lines chip bank 16
224 create_bank chip bank
225 set_label chip bank foobar
233 create_bank chip bank
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/linux/arch/x86/kernel/cpu/mce/
H A Damd.c141 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
145 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
148 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
235 unsigned int bank; member
275 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
282 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
309 __set_bit(bank, data->dfr_intr_banks); in smca_configure()
326 __set_bit(bank, data->thr_intr_banks); in smca_configure()
330 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); in smca_configure()
333 this_cpu_ptr(smca_banks)[bank].paddrv = 1; in smca_configure()
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H A Dintel.c138 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
150 void mce_intel_handle_storm(int bank, bool on) in mce_intel_handle_storm() argument
153 cmci_set_threshold(bank, CMCI_STORM_THRESHOLD); in mce_intel_handle_storm()
155 cmci_set_threshold(bank, cmci_threshold[bank]); in mce_intel_handle_storm()
176 static bool cmci_skip_bank(int bank, u64 *val) in cmci_skip_bank() argument
180 if (test_bit(bank, owned)) in cmci_skip_bank()
184 if (test_bit(bank, mce_banks_ce_disabled)) in cmci_skip_bank()
187 rdmsrq(MSR_IA32_MCx_CTL2(bank), *val); in cmci_skip_bank()
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/linux/drivers/bus/
H A Duniphier-system-bus.c35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
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/linux/drivers/gpu/drm/amd/ras/rascore/
H A Dras_aca_v1_0.c41 struct aca_bank_reg *bank, struct aca_ecc_info *info) in aca_decode_bank_info() argument
46 ipid = bank->regs[ACA_REG_IDX__IPID]; in aca_decode_bank_info()
67 static bool aca_check_bank_hwip(struct aca_bank_reg *bank, enum aca_ecc_hwip type) in aca_check_bank_hwip() argument
73 if (!bank || (type == ACA_ECC_HWIP__UNKNOWN)) in aca_check_bank_hwip()
80 ipid = bank->regs[ACA_REG_IDX__IPID]; in aca_check_bank_hwip()
94 struct aca_bank_reg *bank = (struct aca_bank_reg *)data; in aca_match_gfx_bank() local
97 if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) in aca_match_gfx_bank()
100 instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]); in aca_match_gfx_bank()
116 struct aca_bank_reg *bank = (struct aca_bank_reg *)data; in aca_match_sdma_bank() local
122 if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) in aca_match_sdma_bank()
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/linux/drivers/pinctrl/meson/
H A Dpinctrl-amlogic-a4.c177 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); in aml_pctl_set_function() local
181 unsigned int offset = bank->mux_bit_offs; in aml_pctl_set_function()
185 if (bank->p_mux) { in aml_pctl_set_function()
186 p_mux = bank->p_mux; in aml_pctl_set_function()
188 bank = NULL; in aml_pctl_set_function()
191 bank = &info->banks[i]; in aml_pctl_set_function()
196 if (!bank || !bank->reg_mux) in aml_pctl_set_function()
202 return regmap_update_bits(bank->reg_mux, reg, in aml_pctl_set_function()
208 if (!bank->reg_mux) in aml_pctl_set_function()
212 return regmap_update_bits(bank->reg_mux, reg, in aml_pctl_set_function()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c775 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
778 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
785 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1122 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1125 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1132 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1147 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1149 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1160 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1165 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
[all …]
/linux/drivers/leds/
H A Dleds-tca6507.c159 struct bank { struct
164 } bank[3]; member
175 int bank; /* Bank used, or -1 */ member
278 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument
282 if (bank) { in set_code()
295 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument
297 switch (bank) { in set_level()
300 set_code(tca, TCA6507_MAX_INTENSITY, bank, level); in set_level()
306 tca->bank[bank].level = level; in set_level()
310 static void set_times(struct tca6507_chip *tca, int bank) in set_times() argument
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/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c321 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_in() local
322 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_in()
333 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_out() local
334 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_direction_out()
335 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_out()
354 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_get() local
355 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN; in ma35_gpio_core_get()
362 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_set() local
363 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_set()
378 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_to_request() local
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi12 gpa0: gpa0-gpio-bank {
20 gpa1: gpa1-gpio-bank {
28 gpa2: gpa2-gpio-bank {
36 gpb0: gpb0-gpio-bank {
44 gpb1: gpb1-gpio-bank {
52 gpb2: gpb2-gpio-bank {
60 gpb3: gpb3-gpio-bank {
68 gpc0: gpc0-gpio-bank {
76 gpc3: gpc3-gpio-bank {
84 gpc1: gpc1-gpio-bank {
[all …]

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