| /linux/drivers/gpu/drm/ast/ |
| H A D | ast_ddc.c | 50 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x04); in ast_ddc_algo_bit_data_setsda()
66 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x01); in ast_ddc_algo_bit_data_setscl()
102 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
104 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
109 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
124 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
126 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
131 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
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| H A D | ast_dp501.c | 39 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_ack()
47 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_nack()
57 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_ack()
73 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_nack()
100 waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
159 tmp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd3, 0xff);
269 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ in ast_launch_m68k()
355 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dvo()
450 vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, in ast_init_3rdtx()
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| H A D | ast_main.c | 49 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_detect_widescreen()
88 vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK); in ast_detect_tx_chip()
108 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); in ast_detect_tx_chip()
119 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, in ast_detect_tx_chip()
139 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) == in ast_detect_tx_chip()
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| H A D | ast_mm.c | 42 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xaa, 0xff); in ast_get_vram_size()
58 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xff); in ast_get_vram_size()
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| H A D | ast_dp.c | 18 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, AST_IO_VGACRDF_HPD)) in ast_astdp_is_connected()
201 vgacrdf = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xdf, in __ast_dp_wait_enable()
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| H A D | ast_post.c | 259 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
339 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
1573 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
1645 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
2041 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()
2089 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()
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| H A D | ast_drv.h | 318 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index, in ast_get_index_reg_mask() function
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| H A D | ast_mode.c | 1049 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); in ast_crtc_helper_mode_valid()
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