Searched refs:arfs (Results 1 – 6 of 6) sorted by relevance
162 struct mlx5e_arfs_tables *arfs = mlx5e_fs_get_arfs(fs); in mlx5e_arfs_enable() local168 dest.ft = arfs->arfs_tables[i].ft.t; in mlx5e_arfs_enable()178 set_bit(MLX5E_ARFS_STATE_ENABLED, &arfs->state); in mlx5e_arfs_enable()191 struct mlx5e_arfs_tables *arfs = mlx5e_fs_get_arfs(fs); in _mlx5e_cleanup_tables() local195 destroy_workqueue(arfs->wq); in _mlx5e_cleanup_tables()197 if (!IS_ERR_OR_NULL(arfs->arfs_tables[i].ft.t)) in _mlx5e_cleanup_tables()198 arfs_destroy_table(&arfs->arfs_tables[i]); in _mlx5e_cleanup_tables()204 struct mlx5e_arfs_tables *arfs = mlx5e_fs_get_arfs(fs); in mlx5e_arfs_destroy_tables() local211 kvfree(arfs); in mlx5e_arfs_destroy_tables()218 struct mlx5e_arfs_tables *arfs = mlx5e_fs_get_arfs(fs); in arfs_add_default_rule() local[all …]
73 #define QEDE_ARFS_BUCKET_HEAD(edev, idx) (&(edev)->arfs->arfs_hl_head[idx])132 clear_bit(fltr->sw_id, edev->arfs->arfs_fltr_bmap); in qede_free_arfs_filter()154 edev->arfs->filter_count++; in qede_enqueue_fltr_and_config_searcher()155 if (edev->arfs->filter_count == 1 && in qede_enqueue_fltr_and_config_searcher()156 edev->arfs->mode == QED_FILTER_CONFIG_MODE_DISABLE) { in qede_enqueue_fltr_and_config_searcher()159 edev->arfs->mode = fltr->tuple.mode; in qede_enqueue_fltr_and_config_searcher()175 edev->arfs->filter_count--; in qede_dequeue_fltr_and_config_searcher()176 if (!edev->arfs->filter_count && in qede_dequeue_fltr_and_config_searcher()177 edev->arfs->mode != QED_FILTER_CONFIG_MODE_DISABLE) { in qede_dequeue_fltr_and_config_searcher()182 edev->arfs->mode = QED_FILTER_CONFIG_MODE_DISABLE; in qede_dequeue_fltr_and_config_searcher()[all …]
256 struct qede_arfs *arfs; member
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
184 void mlx5e_fs_set_arfs(struct mlx5e_flow_steering *fs, struct mlx5e_arfs_tables *arfs);
756 } arfs; member