| /linux/drivers/staging/media/meson/vdec/ |
| H A D | vdec_1.c | 57 amvdec_write_dos(core, MPSR, 0); in vdec_1_load_firmware() 58 amvdec_write_dos(core, CPSR, 0); in vdec_1_load_firmware() 62 amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map); in vdec_1_load_firmware() 63 amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4); in vdec_1_load_firmware() 64 amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16))); in vdec_1_load_firmware() 90 amvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0); in vdec_1_stbuf_power_up() 91 amvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0); in vdec_1_stbuf_power_up() 92 amvdec_write_dos(core, POWER_CTL_VLD, BIT(4)); in vdec_1_stbuf_power_up() 94 amvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr); in vdec_1_stbuf_power_up() 95 amvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr); in vdec_1_stbuf_power_up() [all …]
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| H A D | vdec_hevc.c | 59 amvdec_write_dos(core, HEVC_MPSR, 0); in vdec_hevc_load_firmware() 60 amvdec_write_dos(core, HEVC_CPSR, 0); in vdec_hevc_load_firmware() 62 amvdec_write_dos(core, HEVC_IMEM_DMA_ADR, mc_addr_map); in vdec_hevc_load_firmware() 63 amvdec_write_dos(core, HEVC_IMEM_DMA_COUNT, MC_SIZE / 4); in vdec_hevc_load_firmware() 64 amvdec_write_dos(core, HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); in vdec_hevc_load_firmware() 84 amvdec_write_dos(core, HEVC_STREAM_CONTROL, in vdec_hevc_stbuf_init() 86 amvdec_write_dos(core, HEVC_STREAM_START_ADDR, sess->vififo_paddr); in vdec_hevc_stbuf_init() 87 amvdec_write_dos(core, HEVC_STREAM_END_ADDR, in vdec_hevc_stbuf_init() 89 amvdec_write_dos(core, HEVC_STREAM_RD_PTR, sess->vififo_paddr); in vdec_hevc_stbuf_init() 90 amvdec_write_dos(core, HEVC_STREAM_WR_PTR, sess->vififo_paddr); in vdec_hevc_stbuf_init() [all …]
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| H A D | codec_hevc_common.c | 38 amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(31)); in codec_hevc_setup_decode_head() 44 amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4)); in codec_hevc_setup_decode_head() 46 amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0); in codec_hevc_setup_decode_head() 49 amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL2, body_size / 32); in codec_hevc_setup_decode_head() 50 amvdec_write_dos(core, HEVC_CM_BODY_LENGTH, body_size); in codec_hevc_setup_decode_head() 51 amvdec_write_dos(core, HEVC_CM_HEADER_OFFSET, body_size); in codec_hevc_setup_decode_head() 52 amvdec_write_dos(core, HEVC_CM_HEADER_LENGTH, head_size); in codec_hevc_setup_decode_head() 69 amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0); in codec_hevc_setup_buffers_gxbb() 83 amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, in codec_hevc_setup_buffers_gxbb() 88 amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, in codec_hevc_setup_buffers_gxbb() [all …]
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| H A D | codec_vp9.c | 557 amvdec_write_dos(core, HEVC_DBLK_CFG9, thr); in vp9_loop_filter_init() 561 amvdec_write_dos(core, HEVC_DBLK_CFGB, in vp9_loop_filter_init() 568 amvdec_write_dos(core, HEVC_DBLK_CFGB, (0x54 << 8) | BIT(0)); in vp9_loop_filter_init() 570 amvdec_write_dos(core, HEVC_DBLK_CFGB, 0x40400001); in vp9_loop_filter_init() 604 amvdec_write_dos(core, HEVC_DBLK_CFG9, thr); in vp9_loop_filter_frame_init() 660 amvdec_write_dos(core, HEVC_DBLK_CFGA, level); in vp9_loop_filter_frame_init() 719 amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET); in codec_vp9_setup_workspace() 720 amvdec_write_dos(core, VP9_RPM_BUFFER, wkaddr + RPM_OFFSET); in codec_vp9_setup_workspace() 721 amvdec_write_dos(core, VP9_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET); in codec_vp9_setup_workspace() 722 amvdec_write_dos(core, VP9_PPS_BUFFER, wkaddr + PPS_OFFSET); in codec_vp9_setup_workspace() [all …]
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| H A D | vdec_helpers.c | 23 void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val) in amvdec_write_dos() function 27 EXPORT_SYMBOL_GPL(amvdec_write_dos); 31 amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) | val); in amvdec_write_dos_bits() 37 amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) & ~val); in amvdec_clear_dos_bits() 133 amvdec_write_dos(core, reg, in set_canvas_yuv420m() 171 amvdec_write_dos(core, reg, in set_canvas_nv12m()
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| H A D | vdec_helpers.h | 24 void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val);
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