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Searched refs:amdgpu_sriov_vf (Results 1 – 25 of 101) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_virt.h316 #define amdgpu_sriov_vf(adev) \ macro
326 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
329 (amdgpu_sriov_vf((adev)) && \
333 (amdgpu_sriov_vf((adev)) && \
337 (amdgpu_sriov_vf((adev)) && \
341 (amdgpu_sriov_vf((adev)) && \
345 (amdgpu_sriov_vf((adev)) && \
352 (amdgpu_sriov_vf((adev)) && \
387 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
H A Dpsp_v11_0_8.c37 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
70 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
155 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
167 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
H A Dpsp_v3_1.c196 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
257 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
268 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
346 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
357 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
H A Dpsp_v12_0.c178 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
186 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
257 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
269 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
H A Damdgpu_psp.c99 if (amdgpu_sriov_vf(adev)) { in psp_check_pmfw_centralized_cstate_management()
193 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); in psp_early_init()
222 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); in psp_early_init()
246 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); in psp_early_init()
255 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); in psp_early_init()
272 if (amdgpu_sriov_vf(adev)) in psp_early_init()
291 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_free_shared_bufs()
509 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? in psp_sw_init()
731 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); in psp_cmd_submit_buf()
758 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { in psp_cmd_submit_buf()
[all …]
H A Dpsp_v13_0_4.c198 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_stop()
231 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_create()
316 if (amdgpu_sriov_vf(adev)) in psp_v13_0_4_ring_get_wptr()
328 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_set_wptr()
H A Dathub_v1_0.c68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
94 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
H A Damdgpu_device.c786 if (amdgpu_sriov_vf(adev) && in amdgpu_device_xcc_rreg()
917 if (amdgpu_sriov_vf(adev) && in amdgpu_device_xcc_wreg()
1681 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1773 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2546 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) { in amdgpu_device_set_sriov_virtual_display()
2697 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2777 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) in amdgpu_device_ip_early_init()
2779 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_device_ip_early_init()
2785 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2849 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_early_init()
[all …]
H A Dmmhub_v1_0.c115 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
161 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
213 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
353 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
364 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
410 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
429 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
580 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
605 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
H A Damdgpu_vf_error.c36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
H A Dsdma_v5_0.c256 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
628 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
642 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
668 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
701 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume_instance()
760 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_0_gfx_resume_instance()
785 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume_instance()
791 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume_instance()
814 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume_instance()
833 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_0_gfx_resume_instance()
[all …]
H A Dmmhub_v3_0.c172 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_init_system_aperture_regs()
237 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_init_cache_regs()
298 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_disable_identity_aperture()
436 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_fault_enable_default()
622 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_clockgating()
640 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_get_clockgating()
H A Dmmhub_v2_0.c223 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
281 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
342 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
480 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
651 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
676 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
H A Dmmhub_v4_1_0.c169 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_init_system_aperture_regs()
230 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_init_cache_regs()
291 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_disable_identity_aperture()
430 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_set_fault_enable_default()
603 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_set_clockgating()
622 if (amdgpu_sriov_vf(adev)) in mmhub_v4_1_0_get_clockgating()
H A Dgmc_v9_0.c650 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
678 if (!amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
756 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
799 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
858 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { in gmc_v9_0_flush_gpu_tlb()
1549 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) in gmc_v9_0_init_nps_details()
1645 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_late_init()
1680 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) in gmc_v9_0_vram_gtt_location()
1736 if ((!amdgpu_sriov_vf(adev) && in gmc_v9_0_mc_init()
1872 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
[all …]
H A Dpsp_v13_0.c97 if (!amdgpu_sriov_vf(adev)) { in psp_v13_0_init_microcode()
380 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
413 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
498 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
510 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
867 if (amdgpu_sriov_vf(adev)) in psp_v13_0_get_ras_capability()
931 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_reg_program_no_ring()
H A Dpsp_v11_0.c266 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
277 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
297 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
564 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
576 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
H A Dmmhub_v3_0_2.c170 if (!amdgpu_sriov_vf(adev)) { in mmhub_v3_0_2_init_system_aperture_regs()
229 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_init_cache_regs()
290 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_disable_identity_aperture()
428 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_fault_enable_default()
545 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_clockgating()
H A Dsdma_v5_2.c487 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_ctx_switch_enable()
517 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_enable()
550 if (!amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume_instance()
608 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume_instance()
630 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume_instance()
638 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume_instance()
680 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_2_gfx_resume_instance()
822 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1351 !amdgpu_sriov_vf(adev)) in sdma_v5_2_sw_init()
1356 !amdgpu_sriov_vf(adev)) in sdma_v5_2_sw_init()
[all …]
H A Dsoc15.c1229 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1241 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1256 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1281 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1302 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1331 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1338 if ((!amdgpu_sriov_vf(adev)) && in soc15_common_hw_fini()
1423 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1475 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
H A Damdgpu_job.c58 if (!amdgpu_sriov_vf(adev)) in amdgpu_job_core_dump()
67 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { in amdgpu_job_core_dump()
111 if (!amdgpu_sriov_vf(adev)) in amdgpu_job_timedout()
174 if (amdgpu_sriov_vf(adev)) in amdgpu_job_timedout()
H A Dgfxhub_v3_0_3.c157 if (amdgpu_sriov_vf(adev)) in gfxhub_v3_0_3_init_system_aperture_regs()
216 if (amdgpu_sriov_vf(adev)) in gfxhub_v3_0_3_init_cache_regs()
277 if (amdgpu_sriov_vf(adev)) in gfxhub_v3_0_3_disable_identity_aperture()
410 if (amdgpu_sriov_vf(adev)) in gfxhub_v3_0_3_set_fault_enable_default()
H A Djpeg_v4_0.c126 …ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4)… in jpeg_v4_0_sw_init()
148 if (!amdgpu_sriov_vf(adev)) in jpeg_v4_0_sw_init()
189 if (amdgpu_sriov_vf(adev)) { in jpeg_v4_0_hw_init()
225 if (!amdgpu_sriov_vf(adev)) { in jpeg_v4_0_hw_fini()
680 if (amdgpu_sriov_vf(adev)) { in jpeg_v4_0_set_powergating_state()
H A Dsdma_v4_4_2.c148 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
153 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
644 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) in sdma_v4_4_2_inst_enable()
766 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); in sdma_v4_4_2_gfx_resume()
873 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); in sdma_v4_4_2_page_resume()
973 if (amdgpu_sriov_vf(adev)) { in sdma_v4_4_2_inst_start()
1011 if (!amdgpu_sriov_vf(adev)) { in sdma_v4_4_2_inst_start()
1021 if (amdgpu_sriov_vf(adev)) { in sdma_v4_4_2_inst_start()
1560 if (!amdgpu_sriov_vf(adev)) in sdma_v4_4_2_hw_init()
1574 if (amdgpu_sriov_vf(adev)) in sdma_v4_4_2_hw_fini()
[all …]
H A Dgfxhub_v11_5_0.c214 if (amdgpu_sriov_vf(adev)) in gfxhub_v11_5_0_init_cache_regs()
275 if (amdgpu_sriov_vf(adev)) in gfxhub_v11_5_0_disable_identity_aperture()
357 if (amdgpu_sriov_vf(adev)) { in gfxhub_v11_5_0_gart_enable()
425 if (amdgpu_sriov_vf(adev)) in gfxhub_v11_5_0_set_fault_enable_default()

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