| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | jpeg_v2_0.c | 467 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
469 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
471 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
473 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
489 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
491 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
511 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
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| H A D | vcn_sw_ring.c | 32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
52 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
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| H A D | jpeg_v4_0_3.c | 740 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_start()
742 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v4_0_3_dec_ring_insert_start()
744 amdgpu_ring_write(ring, in jpeg_v4_0_3_dec_ring_insert_start()
747 amdgpu_ring_write(ring, 0x80004000); in jpeg_v4_0_3_dec_ring_insert_start()
761 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_end()
763 amdgpu_ring_write(ring, 0x62a04); in jpeg_v4_0_3_dec_ring_insert_end()
765 amdgpu_ring_write(ring, in jpeg_v4_0_3_dec_ring_insert_end()
768 amdgpu_ring_write(ring, 0x00004000); in jpeg_v4_0_3_dec_ring_insert_end()
787 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_emit_fence()
789 amdgpu_ring_write(ring, seq); in jpeg_v4_0_3_dec_ring_emit_fence()
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| H A D | uvd_v7_0.c | 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
549 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
550 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
554 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
555 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
559 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
560 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
563 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
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| H A D | amdgpu_vpe.c | 466 amdgpu_ring_write(ring, ring->funcs->nop | in vpe_ring_insert_nop()
469 amdgpu_ring_write(ring, ring->funcs->nop); in vpe_ring_insert_nop()
494 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | in vpe_ring_emit_pred_exec()
496 amdgpu_ring_write(ring, exec_count & 0x1fff); in vpe_ring_emit_pred_exec()
507 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | in vpe_ring_emit_ib()
511 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); in vpe_ring_emit_ib()
512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vpe_ring_emit_ib()
513 amdgpu_ring_write(ring, ib->length_dw); in vpe_ring_emit_ib()
514 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
515 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
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| H A D | sdma_v6_0.c | 149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v6_0_ring_init_cond_exec()
150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, 1); in sdma_v6_0_ring_init_cond_exec()
156 amdgpu_ring_write(ring, 0); in sdma_v6_0_ring_init_cond_exec()
248 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
251 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v6_0_ring_insert_nop()
282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v6_0_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
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| H A D | sdma_v7_0.c | 149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v7_0_ring_init_cond_exec()
150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, 1); in sdma_v7_0_ring_init_cond_exec()
156 amdgpu_ring_write(ring, 0); in sdma_v7_0_ring_init_cond_exec()
252 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v7_0_ring_insert_nop()
255 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v7_0_ring_insert_nop()
286 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v7_0_ring_emit_ib()
289 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_0_ring_emit_ib()
290 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v7_0_ring_emit_ib()
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| H A D | sdma_v5_2.c | 148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
150 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
151 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
155 amdgpu_ring_write(ring, 0); in sdma_v5_2_ring_init_cond_exec()
262 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
265 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_2_ring_emit_ib()
299 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
300 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
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| H A D | vcn_v1_0.c | 1514 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1516 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1517 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1519 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1533 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1535 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1555 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1557 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1558 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1560 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
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| H A D | vcn_v2_0.c | 1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1487 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1489 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1503 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1504 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1524 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1545 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
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| H A D | sdma_v5_0.c | 308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
309 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
310 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
311 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
315 amdgpu_ring_write(ring, 0); in sdma_v5_0_ring_init_cond_exec()
414 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
417 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
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| H A D | gfx_v8_0.c | 850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
852 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4147 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4148 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4150 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4151 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4152 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4157 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4160 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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| H A D | gfx_v9_0.c | 936 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
937 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
941 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
943 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
945 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx_v9_0_kiq_set_resources()
946 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx_v9_0_kiq_set_resources()
947 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
948 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
958 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
960 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_0_kiq_map_queues()
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| H A D | gfx_v11_0.c | 355 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
356 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
359 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
360 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
361 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx11_kiq_set_resources()
362 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx11_kiq_set_resources()
363 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
364 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
391 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
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| H A D | vce_v4_0.c | 717 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
718 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
719 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
720 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
721 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
729 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
730 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
731 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
732 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
733 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
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| H A D | gfx_v9_4_3.c | 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_4_3_kiq_set_resources()
185 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
189 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
191 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx_v9_4_3_kiq_set_resources()
194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx_v9_4_3_kiq_set_resources()
195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_4_3_kiq_set_resources()
196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_4_3_kiq_set_resources()
207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_4_3_kiq_map_queues()
209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_4_3_kiq_map_queues()
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| H A D | gfx_v12_0.c | 296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_0_kiq_set_resources()
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_0_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_0_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_0_kiq_set_resources()
304 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_0_kiq_set_resources()
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v12_0_kiq_map_queues()
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| H A D | sdma_v4_4_2.c | 358 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_4_2_ring_insert_nop()
361 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_4_2_ring_insert_nop()
384 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_4_2_ring_emit_ib()
387 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_4_2_ring_emit_ib()
388 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_4_2_ring_emit_ib()
389 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_4_2_ring_emit_ib()
390 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
391 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
401 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_4_2_wait_reg_mem()
407 amdgpu_ring_write(ring, addr0); in sdma_v4_4_2_wait_reg_mem()
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| H A D | gfx_v10_0.c | 3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx10_kiq_set_resources()
3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx10_kiq_set_resources()
3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx10_kiq_map_queues()
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| H A D | amdgpu_vce.c | 1072 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1073 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1074 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1075 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1092 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1093 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1094 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1095 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1096 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1097 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
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| H A D | jpeg_v2_5.c | 494 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_start()
496 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v2_6_dec_ring_insert_start()
498 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_start()
500 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); in jpeg_v2_6_dec_ring_insert_start()
512 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_6_dec_ring_insert_end()
514 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v2_6_dec_ring_insert_end()
516 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_6_dec_ring_insert_end()
518 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); in jpeg_v2_6_dec_ring_insert_end()
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| H A D | vcn_v4_0_3.c | 1536 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1537 amdgpu_ring_write(ring, reg << 2); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1538 amdgpu_ring_write(ring, mask); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1539 amdgpu_ring_write(ring, val); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1549 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); in vcn_v4_0_3_enc_ring_emit_wreg()
1550 amdgpu_ring_write(ring, reg << 2); in vcn_v4_0_3_enc_ring_emit_wreg()
1551 amdgpu_ring_write(ring, val); in vcn_v4_0_3_enc_ring_emit_wreg()
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| H A D | amdgpu_vcn.c | 544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); in amdgpu_vcn_dec_ring_test_ring()
545 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_dec_ring_test_ring()
576 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in amdgpu_vcn_dec_sw_ring_test_ring()
881 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in amdgpu_vcn_enc_ring_test_ring()
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| H A D | amdgpu_ring.h | 479 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function
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| H A D | amdgpu_ring.c | 820 amdgpu_ring_write(ring, ring->ring_backup[i]); in amdgpu_ring_reset_helper_end()
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