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Searched refs:amdgpu_ring_write (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_sw_ring.c32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
52 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
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H A Damdgpu_vpe.c491 amdgpu_ring_write(ring, ring->funcs->nop | in vpe_ring_insert_nop()
494 amdgpu_ring_write(ring, ring->funcs->nop); in vpe_ring_insert_nop()
519 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | in vpe_ring_emit_pred_exec()
521 amdgpu_ring_write(ring, exec_count & 0x1fff); in vpe_ring_emit_pred_exec()
532 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | in vpe_ring_emit_ib()
536 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); in vpe_ring_emit_ib()
537 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vpe_ring_emit_ib()
538 amdgpu_ring_write(ring, ib->length_dw); in vpe_ring_emit_ib()
539 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
540 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
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H A Dgfx_v7_0.c2045 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2046 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()
2047 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2088 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2089 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2092 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2093 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2094 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2095 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2096 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
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H A Dsdma_v6_0.c149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v6_0_ring_init_cond_exec()
150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, 1); in sdma_v6_0_ring_init_cond_exec()
156 amdgpu_ring_write(ring, 0); in sdma_v6_0_ring_init_cond_exec()
248 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
251 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v6_0_ring_insert_nop()
282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v6_0_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
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H A Dgfx_v6_0.c1801 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1802 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); in gfx_v6_0_ring_test_ring()
1803 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1820 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1821 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1831 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1832 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1833 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1834 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1835 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
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H A Dgfx_v11_0.c355 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
356 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
359 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
360 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
361 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx11_kiq_set_resources()
362 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx11_kiq_set_resources()
363 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
364 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
391 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
393 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
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H A Dgfx_v12_0.c296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_0_kiq_set_resources()
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_0_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_0_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_0_kiq_set_resources()
304 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_0_kiq_set_resources()
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v12_0_kiq_map_queues()
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H A Dvcn_v4_0_3.c1538 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1539 amdgpu_ring_write(ring, reg << 2); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1540 amdgpu_ring_write(ring, mask); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1541 amdgpu_ring_write(ring, val); in vcn_v4_0_3_enc_ring_emit_reg_wait()
1551 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); in vcn_v4_0_3_enc_ring_emit_wreg()
1552 amdgpu_ring_write(ring, reg << 2); in vcn_v4_0_3_enc_ring_emit_wreg()
1553 amdgpu_ring_write(ring, val); in vcn_v4_0_3_enc_ring_emit_wreg()
H A Damdgpu_jpeg.c171 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0)); in amdgpu_jpeg_dec_ring_test_ring()
172 amdgpu_ring_write(ring, 0xABADCAFE); in amdgpu_jpeg_dec_ring_test_ring()
H A Damdgpu_ring.h486 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function
H A Damdgpu_ring.c890 amdgpu_ring_write(ring, ring->ring_backup[i]); in amdgpu_ring_reset_helper_end()