1 /*
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/kernfs.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_discovery.h"
29 #include "soc15_hw_ip.h"
30 #include "discovery.h"
31 #include "amdgpu_ras.h"
32
33 #include "soc15.h"
34 #include "gfx_v9_0.h"
35 #include "gfx_v9_4_3.h"
36 #include "gmc_v9_0.h"
37 #include "df_v1_7.h"
38 #include "df_v3_6.h"
39 #include "df_v4_3.h"
40 #include "df_v4_6_2.h"
41 #include "df_v4_15.h"
42 #include "nbio_v6_1.h"
43 #include "nbio_v7_0.h"
44 #include "nbio_v7_4.h"
45 #include "nbio_v7_9.h"
46 #include "nbio_v7_11.h"
47 #include "hdp_v4_0.h"
48 #include "vega10_ih.h"
49 #include "vega20_ih.h"
50 #include "sdma_v4_0.h"
51 #include "sdma_v4_4_2.h"
52 #include "uvd_v7_0.h"
53 #include "vce_v4_0.h"
54 #include "vcn_v1_0.h"
55 #include "vcn_v2_5.h"
56 #include "jpeg_v2_5.h"
57 #include "smuio_v9_0.h"
58 #include "gmc_v10_0.h"
59 #include "gmc_v11_0.h"
60 #include "gmc_v12_0.h"
61 #include "gfxhub_v2_0.h"
62 #include "mmhub_v2_0.h"
63 #include "nbio_v2_3.h"
64 #include "nbio_v4_3.h"
65 #include "nbio_v7_2.h"
66 #include "nbio_v7_7.h"
67 #include "nbif_v6_3_1.h"
68 #include "nbio_v6_3_2.h"
69 #include "hdp_v5_0.h"
70 #include "hdp_v5_2.h"
71 #include "hdp_v6_0.h"
72 #include "hdp_v7_0.h"
73 #include "nv.h"
74 #include "soc21.h"
75 #include "soc24.h"
76 #include "soc_v1_0.h"
77 #include "navi10_ih.h"
78 #include "ih_v6_0.h"
79 #include "ih_v6_1.h"
80 #include "ih_v7_0.h"
81 #include "gfx_v10_0.h"
82 #include "gfx_v11_0.h"
83 #include "gfx_v12_0.h"
84 #include "gfx_v12_1.h"
85 #include "sdma_v5_0.h"
86 #include "sdma_v5_2.h"
87 #include "sdma_v6_0.h"
88 #include "sdma_v7_0.h"
89 #include "sdma_v7_1.h"
90 #include "lsdma_v6_0.h"
91 #include "lsdma_v7_0.h"
92 #include "lsdma_v7_1.h"
93 #include "vcn_v2_0.h"
94 #include "jpeg_v2_0.h"
95 #include "vcn_v3_0.h"
96 #include "jpeg_v3_0.h"
97 #include "vcn_v4_0.h"
98 #include "jpeg_v4_0.h"
99 #include "vcn_v4_0_3.h"
100 #include "jpeg_v4_0_3.h"
101 #include "vcn_v4_0_5.h"
102 #include "jpeg_v4_0_5.h"
103 #include "amdgpu_vkms.h"
104 #include "mes_v11_0.h"
105 #include "mes_v12_0.h"
106 #include "mes_v12_1.h"
107 #include "smuio_v11_0.h"
108 #include "smuio_v11_0_6.h"
109 #include "smuio_v13_0.h"
110 #include "smuio_v13_0_3.h"
111 #include "smuio_v13_0_6.h"
112 #include "smuio_v14_0_2.h"
113 #include "smuio_v15_0_0.h"
114 #include "smuio_v15_0_8.h"
115 #include "vcn_v5_0_0.h"
116 #include "vcn_v5_0_1.h"
117 #include "vcn_v5_0_2.h"
118 #include "jpeg_v5_0_0.h"
119 #include "jpeg_v5_0_1.h"
120 #include "jpeg_v5_0_2.h"
121 #include "jpeg_v5_3_0.h"
122
123 #include "amdgpu_ras_mgr.h"
124
125 #include "amdgpu_vpe.h"
126 #if defined(CONFIG_DRM_AMD_ISP)
127 #include "amdgpu_isp.h"
128 #endif
129
130 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
131 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");
132 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");
133 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");
134 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
135 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
136 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
137 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
138 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
139
140 /* Note: These registers are consistent across all the SOCs */
141 #define mmIP_DISCOVERY_VERSION 0x16A00
142 #define mmRCC_CONFIG_MEMSIZE 0xde3
143 #define mmMP0_SMN_C2PMSG_33 0x16061
144 #define mmMM_INDEX 0x0
145 #define mmMM_INDEX_HI 0x6
146 #define mmMM_DATA 0x1
147
148 #define mmDRIVER_SCRATCH_0 0x94
149 #define mmDRIVER_SCRATCH_1 0x95
150 #define mmDRIVER_SCRATCH_2 0x96
151
152 struct ip_discovery_top {
153 struct kobject kobj;
154 struct kset die_kset;
155 struct pci_dev *pdev;
156 struct amdgpu_device *adev;
157 uint8_t *discovery_bin;
158 uint32_t bin_size;
159 bool standalone_mode;
160 };
161
162 /* List to track early-initialized ip_discovery_top entries */
163 struct early_ip_discovery {
164 struct list_head list;
165 struct pci_dev *pdev;
166 struct ip_discovery_top *ip_top;
167 };
168
169 static LIST_HEAD(early_ip_discovery_list);
170 static DEFINE_MUTEX(early_ip_discovery_mutex);
171
172 static const char *hw_id_names[HW_ID_MAX] = {
173 [MP1_HWID] = "MP1",
174 [MP2_HWID] = "MP2",
175 [THM_HWID] = "THM",
176 [SMUIO_HWID] = "SMUIO",
177 [FUSE_HWID] = "FUSE",
178 [CLKA_HWID] = "CLKA",
179 [PWR_HWID] = "PWR",
180 [GC_HWID] = "GC",
181 [UVD_HWID] = "UVD",
182 [AUDIO_AZ_HWID] = "AUDIO_AZ",
183 [ACP_HWID] = "ACP",
184 [DCI_HWID] = "DCI",
185 [DMU_HWID] = "DMU",
186 [DCO_HWID] = "DCO",
187 [DIO_HWID] = "DIO",
188 [XDMA_HWID] = "XDMA",
189 [DCEAZ_HWID] = "DCEAZ",
190 [DAZ_HWID] = "DAZ",
191 [SDPMUX_HWID] = "SDPMUX",
192 [NTB_HWID] = "NTB",
193 [IOHC_HWID] = "IOHC",
194 [L2IMU_HWID] = "L2IMU",
195 [VCE_HWID] = "VCE",
196 [MMHUB_HWID] = "MMHUB",
197 [ATHUB_HWID] = "ATHUB",
198 [DBGU_NBIO_HWID] = "DBGU_NBIO",
199 [DFX_HWID] = "DFX",
200 [DBGU0_HWID] = "DBGU0",
201 [DBGU1_HWID] = "DBGU1",
202 [OSSSYS_HWID] = "OSSSYS",
203 [HDP_HWID] = "HDP",
204 [SDMA0_HWID] = "SDMA0",
205 [SDMA1_HWID] = "SDMA1",
206 [SDMA2_HWID] = "SDMA2",
207 [SDMA3_HWID] = "SDMA3",
208 [LSDMA_HWID] = "LSDMA",
209 [ISP_HWID] = "ISP",
210 [DBGU_IO_HWID] = "DBGU_IO",
211 [DF_HWID] = "DF",
212 [CLKB_HWID] = "CLKB",
213 [FCH_HWID] = "FCH",
214 [DFX_DAP_HWID] = "DFX_DAP",
215 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
216 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
217 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
218 [L1IMU3_HWID] = "L1IMU3",
219 [L1IMU4_HWID] = "L1IMU4",
220 [L1IMU5_HWID] = "L1IMU5",
221 [L1IMU6_HWID] = "L1IMU6",
222 [L1IMU7_HWID] = "L1IMU7",
223 [L1IMU8_HWID] = "L1IMU8",
224 [L1IMU9_HWID] = "L1IMU9",
225 [L1IMU10_HWID] = "L1IMU10",
226 [L1IMU11_HWID] = "L1IMU11",
227 [L1IMU12_HWID] = "L1IMU12",
228 [L1IMU13_HWID] = "L1IMU13",
229 [L1IMU14_HWID] = "L1IMU14",
230 [L1IMU15_HWID] = "L1IMU15",
231 [WAFLC_HWID] = "WAFLC",
232 [FCH_USB_PD_HWID] = "FCH_USB_PD",
233 [PCIE_HWID] = "PCIE",
234 [PCS_HWID] = "PCS",
235 [DDCL_HWID] = "DDCL",
236 [SST_HWID] = "SST",
237 [IOAGR_HWID] = "IOAGR",
238 [NBIF_HWID] = "NBIF",
239 [IOAPIC_HWID] = "IOAPIC",
240 [SYSTEMHUB_HWID] = "SYSTEMHUB",
241 [NTBCCP_HWID] = "NTBCCP",
242 [UMC_HWID] = "UMC",
243 [SATA_HWID] = "SATA",
244 [USB_HWID] = "USB",
245 [CCXSEC_HWID] = "CCXSEC",
246 [XGMI_HWID] = "XGMI",
247 [XGBE_HWID] = "XGBE",
248 [MP0_HWID] = "MP0",
249 [VPE_HWID] = "VPE",
250 [UMSCH_HWID] = "UMSCH",
251 [ATU_HWID] = "ATU",
252 [AIGC_HWID] = "AIGC",
253 };
254
255 static int hw_id_map[MAX_HWIP] = {
256 [GC_HWIP] = GC_HWID,
257 [HDP_HWIP] = HDP_HWID,
258 [SDMA0_HWIP] = SDMA0_HWID,
259 [SDMA1_HWIP] = SDMA1_HWID,
260 [SDMA2_HWIP] = SDMA2_HWID,
261 [SDMA3_HWIP] = SDMA3_HWID,
262 [LSDMA_HWIP] = LSDMA_HWID,
263 [MMHUB_HWIP] = MMHUB_HWID,
264 [ATHUB_HWIP] = ATHUB_HWID,
265 [NBIO_HWIP] = NBIF_HWID,
266 [MP0_HWIP] = MP0_HWID,
267 [MP1_HWIP] = MP1_HWID,
268 [UVD_HWIP] = UVD_HWID,
269 [VCE_HWIP] = VCE_HWID,
270 [DF_HWIP] = DF_HWID,
271 [DCE_HWIP] = DMU_HWID,
272 [OSSSYS_HWIP] = OSSSYS_HWID,
273 [SMUIO_HWIP] = SMUIO_HWID,
274 [PWR_HWIP] = PWR_HWID,
275 [NBIF_HWIP] = NBIF_HWID,
276 [THM_HWIP] = THM_HWID,
277 [CLK_HWIP] = CLKA_HWID,
278 [UMC_HWIP] = UMC_HWID,
279 [XGMI_HWIP] = XGMI_HWID,
280 [DCI_HWIP] = DCI_HWID,
281 [PCIE_HWIP] = PCIE_HWID,
282 [VPE_HWIP] = VPE_HWID,
283 [UMSCH_HWIP] = UMSCH_HWID,
284 [ISP_HWIP] = ISP_HWID,
285 [ATU_HWIP] = ATU_HWID,
286 };
287
amdgpu_discovery_get_tmr_info(struct amdgpu_device * adev,bool * is_tmr_in_sysmem)288 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev,
289 bool *is_tmr_in_sysmem)
290 {
291 u64 vram_size, tmr_offset, tmr_size;
292 u32 msg, tmr_offset_lo, tmr_offset_hi;
293 int i, ret;
294
295 if (!amdgpu_sriov_vf(adev)) {
296 /* It can take up to two second for IFWI init to complete on some dGPUs,
297 * but generally it should be in the 60-100ms range. Normally this starts
298 * as soon as the device gets power so by the time the OS loads this has long
299 * completed. However, when a card is hotplugged via e.g., USB4, we need to
300 * wait for this to complete. Once the C2PMSG is updated, we can
301 * continue.
302 */
303
304 for (i = 0; i < 2000; i++) {
305 msg = RREG32(mmMP0_SMN_C2PMSG_33);
306 if (msg & 0x80000000)
307 break;
308 msleep(1);
309 }
310 }
311
312 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);
313 if (vram_size == U32_MAX)
314 return -ENXIO;
315 else if (!vram_size)
316 *is_tmr_in_sysmem = true;
317 else
318 *is_tmr_in_sysmem = false;
319
320 /* init the default tmr size and offset */
321 adev->discovery.size = DISCOVERY_TMR_SIZE;
322 if (vram_size)
323 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET;
324
325 if (amdgpu_sriov_vf(adev)) {
326 if (adev->virt.is_dynamic_crit_regn_enabled) {
327 adev->discovery.offset =
328 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset;
329 adev->discovery.size =
330 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10;
331 if (!adev->discovery.size)
332 return -EINVAL;
333 } else {
334 goto out;
335 }
336 } else {
337 if (adev->discovery.offset) {
338 u32 signature;
339
340 /* If VRAM holds a valid discovery signature at the default
341 * discovery offset, use it as-is.
342 */
343 amdgpu_device_vram_access(adev, adev->discovery.offset,
344 &signature, sizeof(signature),
345 false);
346 if (le32_to_cpu(signature) == BINARY_SIGNATURE)
347 goto out;
348 }
349
350 tmr_size = RREG32(mmDRIVER_SCRATCH_2);
351 if (tmr_size) {
352 /* It's preferred to transition to PSP mailbox reg interface
353 * for both bare-metal and passthrough if available */
354 adev->discovery.size = (u32)tmr_size;
355 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0);
356 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1);
357 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 |
358 le32_to_cpu(tmr_offset_lo));
359 } else if (!vram_size) {
360 /* fall back to apci approach to query tmr offset if vram_size is 0 */
361 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
362 if (ret)
363 return ret;
364 adev->discovery.size = DISCOVERY_TMR_SIZE;
365 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
366 }
367 }
368 out:
369 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL);
370 if (!adev->discovery.bin)
371 return -ENOMEM;
372 adev->discovery.debugfs_blob.data = adev->discovery.bin;
373 adev->discovery.debugfs_blob.size = adev->discovery.size;
374
375 return 0;
376 }
377
amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device * adev,uint8_t * binary)378 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
379 {
380 void *discv_regn;
381
382 /* This region is read-only and reserved from system use */
383 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC);
384 if (discv_regn) {
385 memcpy(binary, discv_regn, adev->discovery.size);
386 memunmap(discv_regn);
387 return 0;
388 }
389
390 return -ENOENT;
391 }
392
393 #define IP_DISCOVERY_V2 2
394 #define IP_DISCOVERY_V4 4
395
amdgpu_discovery_read_binary_from_mem(struct amdgpu_device * adev,uint8_t * binary,bool is_tmr_in_sysmem)396 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
397 uint8_t *binary,
398 bool is_tmr_in_sysmem)
399 {
400 int ret = 0;
401
402 if (!is_tmr_in_sysmem) {
403 if (amdgpu_sriov_vf(adev) &&
404 amdgpu_sriov_xgmi_connected_to_cpu(adev)) {
405 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
406 } else {
407 amdgpu_device_vram_access(adev, adev->discovery.offset,
408 (uint32_t *)binary,
409 adev->discovery.size, false);
410 adev->discovery.reserve_tmr = true;
411 }
412 } else {
413 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
414 }
415
416 return ret;
417 }
418
amdgpu_discovery_read_binary_from_file(struct amdgpu_device * adev,uint8_t * binary,const char * fw_name)419 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
420 uint8_t *binary,
421 const char *fw_name)
422 {
423 const struct firmware *fw;
424 int r;
425
426 r = firmware_request_nowarn(&fw, fw_name, adev->dev);
427 if (r) {
428 if (amdgpu_discovery == 2)
429 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name);
430 else
431 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name);
432 return r;
433 }
434
435 if (fw->size > adev->discovery.size) {
436 dev_err(adev->dev,
437 "ip discovery firmware \"%s\" too large (%zu > %u)\n",
438 fw_name, fw->size, adev->discovery.size);
439 release_firmware(fw);
440 return -EINVAL;
441 }
442
443 /* Ensure the firmware is at least large enough to contain the
444 * binary header fields.
445 */
446 if (fw->size < offsetof(struct binary_header, binary_size) +
447 sizeof(((struct binary_header *)0)->binary_size)) {
448 dev_err(adev->dev,
449 "ip discovery firmware \"%s\" too small (%zu)\n",
450 fw_name, fw->size);
451 release_firmware(fw);
452 return -EINVAL;
453 }
454
455 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
456 release_firmware(fw);
457
458 return 0;
459 }
460
amdgpu_discovery_calculate_checksum(uint8_t * data,uint32_t size)461 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
462 {
463 uint16_t checksum = 0;
464 int i;
465
466 for (i = 0; i < size; i++)
467 checksum += data[i];
468
469 return checksum;
470 }
471
amdgpu_discovery_verify_checksum(struct amdgpu_device * adev,uint8_t * data,uint32_t size,uint16_t expected)472 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev,
473 uint8_t *data, uint32_t size,
474 uint16_t expected)
475 {
476 uint16_t calculated;
477
478 calculated = amdgpu_discovery_calculate_checksum(data, size);
479
480 if (calculated != expected) {
481 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n",
482 calculated, expected, size);
483 return false;
484 }
485
486 return true;
487 }
488
amdgpu_discovery_verify_binary_signature(uint8_t * binary)489 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
490 {
491 struct binary_header *bhdr;
492 bhdr = (struct binary_header *)binary;
493
494 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
495 }
496
amdgpu_discovery_harvest_config_quirk(struct amdgpu_device * adev)497 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
498 {
499 /*
500 * So far, apply this quirk only on those Navy Flounder boards which
501 * have a bad harvest table of VCN config.
502 */
503 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
504 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
505 switch (adev->pdev->revision) {
506 case 0xC1:
507 case 0xC2:
508 case 0xC3:
509 case 0xC5:
510 case 0xC7:
511 case 0xCF:
512 case 0xDF:
513 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
514 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
515 break;
516 default:
517 break;
518 }
519 }
520 }
521
amdgpu_discovery_verify_npsinfo(struct amdgpu_device * adev,struct table_info * info)522 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
523 struct table_info *info)
524 {
525 uint8_t *discovery_bin = adev->discovery.bin;
526 uint16_t checksum;
527 uint16_t offset;
528
529 offset = le16_to_cpu(info->offset);
530 checksum = le16_to_cpu(info->checksum);
531
532 struct nps_info_header *nhdr =
533 (struct nps_info_header *)(discovery_bin + offset);
534
535 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
536 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
537 return -EINVAL;
538 }
539
540 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
541 le32_to_cpu(nhdr->size_bytes),
542 checksum)) {
543 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
544 return -EINVAL;
545 }
546
547 return 0;
548 }
549
amdgpu_discovery_get_fw_name(struct amdgpu_device * adev)550 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)
551 {
552 if (amdgpu_discovery == 2) {
553 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */
554 adev->discovery.reserve_tmr = true;
555 return "amdgpu/ip_discovery.bin";
556 }
557
558 switch (adev->asic_type) {
559 case CHIP_VEGA10:
560 return "amdgpu/vega10_ip_discovery.bin";
561 case CHIP_VEGA12:
562 return "amdgpu/vega12_ip_discovery.bin";
563 case CHIP_RAVEN:
564 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
565 return "amdgpu/raven2_ip_discovery.bin";
566 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
567 return "amdgpu/picasso_ip_discovery.bin";
568 else
569 return "amdgpu/raven_ip_discovery.bin";
570 case CHIP_VEGA20:
571 return "amdgpu/vega20_ip_discovery.bin";
572 case CHIP_ARCTURUS:
573 return "amdgpu/arcturus_ip_discovery.bin";
574 case CHIP_ALDEBARAN:
575 return "amdgpu/aldebaran_ip_discovery.bin";
576 default:
577 return NULL;
578 }
579 }
580
581 static struct table_info *
amdgpu_discovery_get_table_info_from_bin(uint8_t * discovery_bin,uint16_t table_id)582 amdgpu_discovery_get_table_info_from_bin(uint8_t *discovery_bin,
583 uint16_t table_id)
584 {
585 struct binary_header *bhdr = (struct binary_header *)discovery_bin;
586 struct binary_header_v2 *bhdrv2;
587
588 switch (bhdr->version_major) {
589 case 2:
590 bhdrv2 = (struct binary_header_v2 *)discovery_bin;
591 return &bhdrv2->table_list[table_id];
592 case 1:
593 case 0:
594 return &bhdr->table_list[table_id];
595 default:
596 return NULL;
597 }
598 }
599
amdgpu_discovery_get_table_info(struct amdgpu_device * adev,struct table_info ** info,uint16_t table_id)600 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev,
601 struct table_info **info,
602 uint16_t table_id)
603 {
604 struct binary_header *bhdr =
605 (struct binary_header *)adev->discovery.bin;
606
607 *info = amdgpu_discovery_get_table_info_from_bin(adev->discovery.bin,
608 table_id);
609 if (!*info) {
610 dev_err(adev->dev, "Invalid ip discovery table version %d\n",
611 bhdr->version_major);
612 return -EINVAL;
613 }
614
615 return 0;
616 }
617
amdgpu_discovery_table_check(struct amdgpu_device * adev,uint8_t * discovery_bin,uint16_t table_id)618 static int amdgpu_discovery_table_check(struct amdgpu_device *adev,
619 uint8_t *discovery_bin,
620 uint16_t table_id)
621 {
622 int r, act_val, exp_val, table_size;
623 uint16_t offset, checksum;
624 struct table_info *info;
625 bool check_table = true;
626 char *table_name;
627
628 r = amdgpu_discovery_get_table_info(adev, &info, table_id);
629 if (r)
630 return r;
631 offset = le16_to_cpu(info->offset);
632 checksum = le16_to_cpu(info->checksum);
633
634 switch (table_id) {
635 case IP_DISCOVERY: {
636 struct ip_discovery_header *ihdr =
637 (struct ip_discovery_header *)(discovery_bin + offset);
638 act_val = le32_to_cpu(ihdr->signature);
639 exp_val = DISCOVERY_TABLE_SIGNATURE;
640 table_size = le16_to_cpu(ihdr->size);
641 table_name = "data table";
642 break;
643 }
644 case GC: {
645 struct gpu_info_header *ghdr =
646 (struct gpu_info_header *)(discovery_bin + offset);
647 act_val = le32_to_cpu(ghdr->table_id);
648 exp_val = GC_TABLE_ID;
649 table_size = le16_to_cpu(ghdr->size);
650 table_name = "gc table";
651 break;
652 }
653 case HARVEST_INFO: {
654 struct harvest_info_header *hhdr =
655 (struct harvest_info_header *)(discovery_bin + offset);
656 act_val = le32_to_cpu(hhdr->signature);
657 exp_val = HARVEST_TABLE_SIGNATURE;
658 table_size = sizeof(struct harvest_table);
659 table_name = "harvest table";
660 break;
661 }
662 case VCN_INFO: {
663 struct vcn_info_header *vhdr =
664 (struct vcn_info_header *)(discovery_bin + offset);
665 act_val = le32_to_cpu(vhdr->table_id);
666 exp_val = VCN_INFO_TABLE_ID;
667 table_size = le32_to_cpu(vhdr->size_bytes);
668 table_name = "vcn table";
669 break;
670 }
671 case MALL_INFO: {
672 struct mall_info_header *mhdr =
673 (struct mall_info_header *)(discovery_bin + offset);
674 act_val = le32_to_cpu(mhdr->table_id);
675 exp_val = MALL_INFO_TABLE_ID;
676 table_size = le32_to_cpu(mhdr->size_bytes);
677 table_name = "mall table";
678 check_table = false;
679 break;
680 }
681 default:
682 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id);
683 check_table = false;
684 break;
685 }
686
687 if (check_table && offset) {
688 if (act_val != exp_val) {
689 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name);
690 return -EINVAL;
691 }
692
693 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset,
694 table_size, checksum)) {
695 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name);
696 return -EINVAL;
697 }
698 }
699
700 return 0;
701 }
702
amdgpu_discovery_init(struct amdgpu_device * adev)703 static int amdgpu_discovery_init(struct amdgpu_device *adev)
704 {
705 struct binary_header *bhdr;
706 uint8_t *discovery_bin;
707 const char *fw_name;
708 uint16_t offset;
709 uint16_t size;
710 uint16_t checksum;
711 uint16_t table_id;
712 bool is_tmr_in_sysmem;
713 int r;
714
715 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem);
716 if (r)
717 return r;
718
719 discovery_bin = adev->discovery.bin;
720 /* Read from file if it is the preferred option */
721 fw_name = amdgpu_discovery_get_fw_name(adev);
722 if (fw_name != NULL) {
723 drm_dbg(&adev->ddev, "use ip discovery information from file");
724 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin,
725 fw_name);
726 if (r)
727 goto out;
728 } else {
729 drm_dbg(&adev->ddev, "use ip discovery information from memory");
730 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin,
731 is_tmr_in_sysmem);
732 if (r)
733 goto out;
734 }
735
736 /* check the ip discovery binary signature */
737 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) {
738 dev_err(adev->dev,
739 "get invalid ip discovery binary signature\n");
740 r = -EINVAL;
741 goto out;
742 }
743
744 bhdr = (struct binary_header *)discovery_bin;
745
746 offset = offsetof(struct binary_header, binary_checksum) +
747 sizeof(bhdr->binary_checksum);
748 size = le16_to_cpu(bhdr->binary_size) - offset;
749 checksum = le16_to_cpu(bhdr->binary_checksum);
750
751 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size,
752 checksum)) {
753 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
754 r = -EINVAL;
755 goto out;
756 }
757
758 for (table_id = 0; table_id <= MALL_INFO; table_id++) {
759 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id);
760 if (r)
761 goto out;
762 }
763
764 return 0;
765
766 out:
767 kfree(adev->discovery.bin);
768 adev->discovery.bin = NULL;
769 if ((amdgpu_discovery != 2) &&
770 (RREG32(mmIP_DISCOVERY_VERSION) == 4))
771 amdgpu_ras_query_boot_status(adev, 4);
772 return r;
773 }
774
amdgpu_discovery_fini(struct amdgpu_device * adev)775 void amdgpu_discovery_fini(struct amdgpu_device *adev)
776 {
777 if (adev->discovery.ip_top && !adev->discovery.ip_top->standalone_mode)
778 amdgpu_discovery_sysfs_fini(adev);
779
780 kfree(adev->discovery.bin);
781 adev->discovery.bin = NULL;
782 }
783
amdgpu_discovery_validate_ip(struct amdgpu_device * adev,uint8_t instance,uint16_t hw_id)784 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,
785 uint8_t instance, uint16_t hw_id)
786 {
787 if (instance >= HWIP_MAX_INSTANCE) {
788 if (adev)
789 dev_err(adev->dev,
790 "Unexpected instance_number (%d) from ip discovery blob\n",
791 instance);
792 return -EINVAL;
793 }
794 if (hw_id >= HW_ID_MAX) {
795 if (adev)
796 dev_err(adev->dev,
797 "Unexpected hw_id (%d) from ip discovery blob\n",
798 hw_id);
799 return -EINVAL;
800 }
801
802 return 0;
803 }
804
amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device * adev,uint32_t * vcn_harvest_count)805 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
806 uint32_t *vcn_harvest_count)
807 {
808 uint8_t *discovery_bin = adev->discovery.bin;
809 struct binary_header *bhdr;
810 struct ip_discovery_header *ihdr;
811 struct die_header *dhdr;
812 struct ip *ip;
813 uint16_t die_offset, ip_offset, num_dies, num_ips;
814 uint16_t hw_id;
815 uint8_t inst;
816 int i, j;
817
818 bhdr = (struct binary_header *)discovery_bin;
819 ihdr = (struct ip_discovery_header
820 *)(discovery_bin +
821 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
822 num_dies = le16_to_cpu(ihdr->num_dies);
823
824 /* scan harvest bit of all IP data structures */
825 for (i = 0; i < num_dies; i++) {
826 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
827 dhdr = (struct die_header *)(discovery_bin + die_offset);
828 num_ips = le16_to_cpu(dhdr->num_ips);
829 ip_offset = die_offset + sizeof(*dhdr);
830
831 for (j = 0; j < num_ips; j++) {
832 ip = (struct ip *)(discovery_bin + ip_offset);
833 inst = ip->number_instance;
834 hw_id = le16_to_cpu(ip->hw_id);
835 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
836 goto next_ip;
837
838 if (ip->harvest == 1) {
839 switch (hw_id) {
840 case VCN_HWID:
841 (*vcn_harvest_count)++;
842 if (inst == 0) {
843 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
844 adev->vcn.inst_mask &=
845 ~AMDGPU_VCN_HARVEST_VCN0;
846 adev->jpeg.inst_mask &=
847 ~AMDGPU_VCN_HARVEST_VCN0;
848 } else {
849 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
850 adev->vcn.inst_mask &=
851 ~AMDGPU_VCN_HARVEST_VCN1;
852 adev->jpeg.inst_mask &=
853 ~AMDGPU_VCN_HARVEST_VCN1;
854 }
855 break;
856 case DMU_HWID:
857 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
858 break;
859 default:
860 break;
861 }
862 }
863 next_ip:
864 ip_offset += struct_size(ip, base_address,
865 ip->num_base_address);
866 }
867 }
868 }
869
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device * adev,uint32_t * vcn_harvest_count,uint32_t * umc_harvest_count)870 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
871 uint32_t *vcn_harvest_count,
872 uint32_t *umc_harvest_count)
873 {
874 uint8_t *discovery_bin = adev->discovery.bin;
875 struct table_info *info;
876 struct harvest_table *harvest_info;
877 u16 offset;
878 int i;
879 u64 umc_harvest_config = 0;
880
881 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO))
882 return;
883 offset = le16_to_cpu(info->offset);
884
885 if (!offset) {
886 dev_err(adev->dev, "invalid harvest table offset\n");
887 return;
888 }
889
890 harvest_info = (struct harvest_table *)(discovery_bin + offset);
891
892 for (i = 0; i < 32; i++) {
893 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id);
894 u8 inst = harvest_info->list[i].number_instance;
895
896 if (hw_id == 0)
897 break;
898
899 if (inst >= 32) {
900 dev_warn(adev->dev,
901 "bogus harvest instance %u for hw_id %u\n",
902 inst, hw_id);
903 continue;
904 }
905
906 switch (hw_id) {
907 case VCN_HWID:
908 (*vcn_harvest_count)++;
909 adev->vcn.harvest_config |= BIT(inst);
910 adev->jpeg.harvest_config |= BIT(inst);
911
912 adev->vcn.inst_mask &= ~BIT(inst);
913 adev->jpeg.inst_mask &= ~BIT(inst);
914 break;
915 case DMU_HWID:
916 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
917 break;
918 case UMC_HWID:
919 umc_harvest_config |= BIT_ULL(inst);
920 (*umc_harvest_count)++;
921 break;
922 case GC_HWID:
923 adev->gfx.xcc_mask &= ~BIT(inst);
924 break;
925 case SDMA0_HWID:
926 adev->sdma.sdma_mask &= ~BIT(inst);
927 break;
928 #if defined(CONFIG_DRM_AMD_ISP)
929 case ISP_HWID:
930 adev->isp.harvest_config |= ~BIT(inst);
931 break;
932 #endif
933 default:
934 break;
935 }
936 }
937
938 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) &
939 ~umc_harvest_config;
940 }
941
942 /* ================================================== */
943
944 struct ip_hw_instance {
945 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
946
947 int hw_id;
948 u8 num_instance;
949 u8 major, minor, revision;
950 u8 harvest;
951
952 int num_base_addresses;
953 u32 base_addr[] __counted_by(num_base_addresses);
954 };
955
956 struct ip_hw_id {
957 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
958 int hw_id;
959 };
960
961 struct ip_die_entry {
962 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
963 u16 num_ips;
964 };
965
966 /* -------------------------------------------------- */
967
968 struct ip_hw_instance_attr {
969 struct attribute attr;
970 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
971 };
972
hw_id_show(struct ip_hw_instance * ip_hw_instance,char * buf)973 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
974 {
975 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
976 }
977
num_instance_show(struct ip_hw_instance * ip_hw_instance,char * buf)978 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
979 {
980 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
981 }
982
major_show(struct ip_hw_instance * ip_hw_instance,char * buf)983 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
984 {
985 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
986 }
987
minor_show(struct ip_hw_instance * ip_hw_instance,char * buf)988 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
989 {
990 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
991 }
992
revision_show(struct ip_hw_instance * ip_hw_instance,char * buf)993 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
994 {
995 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
996 }
997
harvest_show(struct ip_hw_instance * ip_hw_instance,char * buf)998 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
999 {
1000 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
1001 }
1002
num_base_addresses_show(struct ip_hw_instance * ip_hw_instance,char * buf)1003 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1004 {
1005 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
1006 }
1007
base_addr_show(struct ip_hw_instance * ip_hw_instance,char * buf)1008 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
1009 {
1010 ssize_t at;
1011 int ii;
1012
1013 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
1014 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
1015 */
1016 if (at + 12 > PAGE_SIZE)
1017 break;
1018 at += sysfs_emit_at(buf, at, "0x%08X\n",
1019 ip_hw_instance->base_addr[ii]);
1020 }
1021
1022 return at;
1023 }
1024
1025 static struct ip_hw_instance_attr ip_hw_attr[] = {
1026 __ATTR_RO(hw_id),
1027 __ATTR_RO(num_instance),
1028 __ATTR_RO(major),
1029 __ATTR_RO(minor),
1030 __ATTR_RO(revision),
1031 __ATTR_RO(harvest),
1032 __ATTR_RO(num_base_addresses),
1033 __ATTR_RO(base_addr),
1034 };
1035
1036 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
1037 ATTRIBUTE_GROUPS(ip_hw_instance);
1038
1039 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
1040 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
1041
ip_hw_instance_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1042 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
1043 struct attribute *attr,
1044 char *buf)
1045 {
1046 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1047 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
1048
1049 if (!ip_hw_attr->show)
1050 return -EIO;
1051
1052 return ip_hw_attr->show(ip_hw_instance, buf);
1053 }
1054
1055 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
1056 .show = ip_hw_instance_attr_show,
1057 };
1058
ip_hw_instance_release(struct kobject * kobj)1059 static void ip_hw_instance_release(struct kobject *kobj)
1060 {
1061 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
1062
1063 kfree(ip_hw_instance);
1064 }
1065
1066 static const struct kobj_type ip_hw_instance_ktype = {
1067 .release = ip_hw_instance_release,
1068 .sysfs_ops = &ip_hw_instance_sysfs_ops,
1069 .default_groups = ip_hw_instance_groups,
1070 };
1071
1072 /* -------------------------------------------------- */
1073
1074 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
1075
ip_hw_id_release(struct kobject * kobj)1076 static void ip_hw_id_release(struct kobject *kobj)
1077 {
1078 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
1079
1080 if (!list_empty(&ip_hw_id->hw_id_kset.list))
1081 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
1082 kfree(ip_hw_id);
1083 }
1084
1085 static const struct kobj_type ip_hw_id_ktype = {
1086 .release = ip_hw_id_release,
1087 .sysfs_ops = &kobj_sysfs_ops,
1088 };
1089
1090 /* -------------------------------------------------- */
1091
1092 static void die_kobj_release(struct kobject *kobj);
1093 static void ip_disc_release(struct kobject *kobj);
1094
1095 struct ip_die_entry_attribute {
1096 struct attribute attr;
1097 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
1098 };
1099
1100 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
1101
num_ips_show(struct ip_die_entry * ip_die_entry,char * buf)1102 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
1103 {
1104 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
1105 }
1106
1107 /* If there are more ip_die_entry attrs, other than the number of IPs,
1108 * we can make this intro an array of attrs, and then initialize
1109 * ip_die_entry_attrs in a loop.
1110 */
1111 static struct ip_die_entry_attribute num_ips_attr =
1112 __ATTR_RO(num_ips);
1113
1114 static struct attribute *ip_die_entry_attrs[] = {
1115 &num_ips_attr.attr,
1116 NULL,
1117 };
1118 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
1119
1120 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
1121
ip_die_entry_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)1122 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
1123 struct attribute *attr,
1124 char *buf)
1125 {
1126 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
1127 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1128
1129 if (!ip_die_entry_attr->show)
1130 return -EIO;
1131
1132 return ip_die_entry_attr->show(ip_die_entry, buf);
1133 }
1134
ip_die_entry_release(struct kobject * kobj)1135 static void ip_die_entry_release(struct kobject *kobj)
1136 {
1137 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
1138
1139 if (!list_empty(&ip_die_entry->ip_kset.list))
1140 DRM_ERROR("ip_die_entry->ip_kset is not empty");
1141 kfree(ip_die_entry);
1142 }
1143
1144 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
1145 .show = ip_die_entry_attr_show,
1146 };
1147
1148 static const struct kobj_type ip_die_entry_ktype = {
1149 .release = ip_die_entry_release,
1150 .sysfs_ops = &ip_die_entry_sysfs_ops,
1151 .default_groups = ip_die_entry_groups,
1152 };
1153
1154 static const struct kobj_type die_kobj_ktype = {
1155 .release = die_kobj_release,
1156 .sysfs_ops = &kobj_sysfs_ops,
1157 };
1158
1159 static const struct kobj_type ip_discovery_ktype = {
1160 .release = ip_disc_release,
1161 .sysfs_ops = &kobj_sysfs_ops,
1162 };
1163
die_kobj_release(struct kobject * kobj)1164 static void die_kobj_release(struct kobject *kobj)
1165 {
1166 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
1167 struct ip_discovery_top,
1168 die_kset);
1169 if (!list_empty(&ip_top->die_kset.list))
1170 DRM_ERROR("ip_top->die_kset is not empty");
1171 }
1172
ip_disc_release(struct kobject * kobj)1173 static void ip_disc_release(struct kobject *kobj)
1174 {
1175 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
1176 kobj);
1177 struct amdgpu_device *adev = ip_top->adev;
1178
1179 /* In standalone mode, discovery_bin is managed by devm and will be
1180 * freed automatically when the PCI device is removed. Do not manually
1181 * free it here to avoid double-free.
1182 */
1183
1184 kfree(ip_top);
1185 if (adev)
1186 adev->discovery.ip_top = NULL;
1187 }
1188
amdgpu_discovery_get_harvest_info(struct amdgpu_device * adev,uint16_t hw_id,uint8_t inst)1189 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
1190 uint16_t hw_id, uint8_t inst)
1191 {
1192 uint8_t harvest = 0;
1193
1194 /* In early init mode (adev == NULL), harvest info is not available */
1195 if (!adev)
1196 return 0;
1197
1198 /* Until a uniform way is figured, get mask based on hwid */
1199 switch (hw_id) {
1200 case VCN_HWID:
1201 /* VCN vs UVD+VCE */
1202 if (!amdgpu_ip_version(adev, VCE_HWIP, 0))
1203 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
1204 break;
1205 case DMU_HWID:
1206 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
1207 harvest = 0x1;
1208 break;
1209 case UMC_HWID:
1210 /* TODO: It needs another parsing; for now, ignore.*/
1211 break;
1212 case GC_HWID:
1213 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1214 break;
1215 case SDMA0_HWID:
1216 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 return harvest;
1223 }
1224
amdgpu_discovery_sysfs_ips(struct amdgpu_device * adev,struct ip_discovery_top * ip_top,struct ip_die_entry * ip_die_entry,const size_t _ip_offset,const int num_ips,bool reg_base_64)1225 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1226 struct ip_discovery_top *ip_top,
1227 struct ip_die_entry *ip_die_entry,
1228 const size_t _ip_offset, const int num_ips,
1229 bool reg_base_64)
1230 {
1231 uint8_t *discovery_bin = ip_top->standalone_mode ?
1232 ip_top->discovery_bin :
1233 adev->discovery.bin;
1234 int ii, jj, kk, res;
1235 uint16_t hw_id;
1236 uint8_t inst;
1237
1238 DRM_DEBUG("num_ips:%d", num_ips);
1239
1240 /* Find all IPs of a given HW ID, and add their instance to
1241 * #die/#hw_id/#instance/<attributes>
1242 */
1243 for (ii = 0; ii < HW_ID_MAX; ii++) {
1244 struct ip_hw_id *ip_hw_id = NULL;
1245 size_t ip_offset = _ip_offset;
1246
1247 for (jj = 0; jj < num_ips; jj++) {
1248 struct ip_v4 *ip;
1249 struct ip_hw_instance *ip_hw_instance;
1250
1251 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1252 inst = ip->instance_number;
1253 hw_id = le16_to_cpu(ip->hw_id);
1254 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
1255 hw_id != ii)
1256 goto next_ip;
1257
1258 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1259
1260 /* We have a hw_id match; register the hw
1261 * block if not yet registered.
1262 */
1263 if (!ip_hw_id) {
1264 ip_hw_id = kzalloc_obj(*ip_hw_id);
1265 if (!ip_hw_id)
1266 return -ENOMEM;
1267 ip_hw_id->hw_id = ii;
1268
1269 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1270 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1271 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1272 res = kset_register(&ip_hw_id->hw_id_kset);
1273 if (res) {
1274 DRM_ERROR("Couldn't register ip_hw_id kset");
1275 kfree(ip_hw_id);
1276 return res;
1277 }
1278 if (hw_id_names[ii]) {
1279 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1280 &ip_hw_id->hw_id_kset.kobj,
1281 hw_id_names[ii]);
1282 if (res) {
1283 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1284 hw_id_names[ii],
1285 kobject_name(&ip_die_entry->ip_kset.kobj));
1286 }
1287 }
1288 }
1289
1290 /* Now register its instance.
1291 */
1292 ip_hw_instance = kzalloc_flex(*ip_hw_instance,
1293 base_addr,
1294 ip->num_base_address);
1295 if (!ip_hw_instance) {
1296 DRM_ERROR("no memory for ip_hw_instance");
1297 return -ENOMEM;
1298 }
1299 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1300 ip_hw_instance->num_instance = ip->instance_number;
1301 ip_hw_instance->major = ip->major;
1302 ip_hw_instance->minor = ip->minor;
1303 ip_hw_instance->revision = ip->revision;
1304 ip_hw_instance->harvest =
1305 amdgpu_discovery_get_harvest_info(
1306 adev, ip_hw_instance->hw_id,
1307 ip_hw_instance->num_instance);
1308 ip_hw_instance->num_base_addresses = ip->num_base_address;
1309
1310 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1311 /*
1312 * Standalone mode uses a raw copy of the discovery
1313 * binary; decode 64-bit addresses here. The shared
1314 * bin is already collapsed to 32-bit in place.
1315 */
1316 if (reg_base_64 && ip_top->standalone_mode)
1317 ip_hw_instance->base_addr[kk] =
1318 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1319 else
1320 ip_hw_instance->base_addr[kk] =
1321 le32_to_cpu(ip->base_address[kk]);
1322 }
1323
1324 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1325 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1326 res = kobject_add(&ip_hw_instance->kobj, NULL,
1327 "%d", ip_hw_instance->num_instance);
1328 next_ip:
1329 if (reg_base_64)
1330 ip_offset += struct_size(ip, base_address_64,
1331 ip->num_base_address);
1332 else
1333 ip_offset += struct_size(ip, base_address,
1334 ip->num_base_address);
1335 }
1336 }
1337
1338 return 0;
1339 }
1340
amdgpu_discovery_sysfs_recurse(struct amdgpu_device * adev,struct ip_discovery_top * ip_top)1341 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev,
1342 struct ip_discovery_top *ip_top)
1343 {
1344 uint8_t *discovery_bin = ip_top->standalone_mode ?
1345 ip_top->discovery_bin :
1346 adev->discovery.bin;
1347 struct table_info *info;
1348 struct ip_discovery_header *ihdr;
1349 struct die_header *dhdr;
1350 struct kset *die_kset = &ip_top->die_kset;
1351 u16 num_dies, die_offset, num_ips;
1352 size_t ip_offset;
1353 int ii, res;
1354
1355 info = amdgpu_discovery_get_table_info_from_bin(discovery_bin,
1356 IP_DISCOVERY);
1357 if (!info)
1358 return -EINVAL;
1359 ihdr = (struct ip_discovery_header
1360 *)(discovery_bin +
1361 le16_to_cpu(info->offset));
1362 num_dies = le16_to_cpu(ihdr->num_dies);
1363
1364 DRM_DEBUG("number of dies: %d\n", num_dies);
1365
1366 for (ii = 0; ii < num_dies; ii++) {
1367 struct ip_die_entry *ip_die_entry;
1368
1369 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1370 dhdr = (struct die_header *)(discovery_bin + die_offset);
1371 num_ips = le16_to_cpu(dhdr->num_ips);
1372 ip_offset = die_offset + sizeof(*dhdr);
1373
1374 /* Add the die to the kset.
1375 *
1376 * dhdr->die_id == ii, which was checked in
1377 * amdgpu_discovery_reg_base_init().
1378 */
1379
1380 ip_die_entry = kzalloc_obj(*ip_die_entry);
1381 if (!ip_die_entry)
1382 return -ENOMEM;
1383
1384 ip_die_entry->num_ips = num_ips;
1385
1386 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1387 ip_die_entry->ip_kset.kobj.kset = die_kset;
1388 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1389 res = kset_register(&ip_die_entry->ip_kset);
1390 if (res) {
1391 DRM_ERROR("Couldn't register ip_die_entry kset");
1392 kfree(ip_die_entry);
1393 return res;
1394 }
1395
1396 amdgpu_discovery_sysfs_ips(adev, ip_top, ip_die_entry, ip_offset,
1397 num_ips, !!ihdr->base_addr_64_bit);
1398 }
1399
1400 return 0;
1401 }
1402
amdgpu_discovery_sysfs_init(struct amdgpu_device * adev)1403 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1404 {
1405 uint8_t *discovery_bin = adev->discovery.bin;
1406 struct ip_discovery_top *ip_top;
1407 struct kset *die_kset;
1408 int res, ii;
1409
1410 if (!discovery_bin)
1411 return -EINVAL;
1412
1413 /* If early init already created sysfs in standalone mode, skip normal init */
1414 if (adev->discovery.ip_top && adev->discovery.ip_top->standalone_mode)
1415 return 0;
1416
1417 ip_top = kzalloc_obj(*ip_top);
1418 if (!ip_top)
1419 return -ENOMEM;
1420
1421 ip_top->adev = adev;
1422
1423 /* Check if ip_discovery already exists before creating.
1424 * This shouldn't normally happen but handle it gracefully.
1425 */
1426 if (adev->dev->kobj.sd) {
1427 struct kernfs_node *existing;
1428
1429 existing = kernfs_find_and_get(adev->dev->kobj.sd, "ip_discovery");
1430 if (existing) {
1431 kernfs_put(existing);
1432 kfree(ip_top);
1433 return 0;
1434 }
1435 }
1436
1437 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1438 &adev->dev->kobj, "ip_discovery");
1439 if (res) {
1440 DRM_ERROR("Couldn't init and add ip_discovery/");
1441 goto Err;
1442 }
1443
1444 adev->discovery.ip_top = ip_top;
1445
1446 die_kset = &ip_top->die_kset;
1447 kobject_set_name(&die_kset->kobj, "%s", "die");
1448 die_kset->kobj.parent = &ip_top->kobj;
1449 die_kset->kobj.ktype = &die_kobj_ktype;
1450 res = kset_register(&ip_top->die_kset);
1451 if (res) {
1452 DRM_ERROR("Couldn't register die_kset");
1453 goto Err;
1454 }
1455
1456 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1457 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1458 ip_hw_instance_attrs[ii] = NULL;
1459
1460 res = amdgpu_discovery_sysfs_recurse(adev, ip_top);
1461
1462 return res;
1463 Err:
1464 kobject_put(&ip_top->kobj);
1465 return res;
1466 }
1467
1468 /* -------------------------------------------------- */
1469
1470 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1471
amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id * ip_hw_id)1472 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1473 {
1474 struct list_head *el, *tmp;
1475 struct kset *hw_id_kset;
1476
1477 hw_id_kset = &ip_hw_id->hw_id_kset;
1478 spin_lock(&hw_id_kset->list_lock);
1479 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1480 list_del_init(el);
1481 spin_unlock(&hw_id_kset->list_lock);
1482 /* kobject is embedded in ip_hw_instance */
1483 kobject_put(list_to_kobj(el));
1484 spin_lock(&hw_id_kset->list_lock);
1485 }
1486 spin_unlock(&hw_id_kset->list_lock);
1487 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1488 }
1489
amdgpu_discovery_sysfs_die_free(struct ip_die_entry * ip_die_entry)1490 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1491 {
1492 struct list_head *el, *tmp;
1493 struct kset *ip_kset;
1494
1495 ip_kset = &ip_die_entry->ip_kset;
1496 spin_lock(&ip_kset->list_lock);
1497 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1498 list_del_init(el);
1499 spin_unlock(&ip_kset->list_lock);
1500 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1501 spin_lock(&ip_kset->list_lock);
1502 }
1503 spin_unlock(&ip_kset->list_lock);
1504 kobject_put(&ip_die_entry->ip_kset.kobj);
1505 }
1506
amdgpu_discovery_sysfs_fini(struct amdgpu_device * adev)1507 void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1508 {
1509 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1510 struct list_head *el, *tmp;
1511 struct kset *die_kset;
1512
1513 if (!ip_top)
1514 return;
1515
1516 /*
1517 * In standalone mode the sysfs hierarchy is tied to the PCI device
1518 * lifetime and is torn down by amdgpu_discovery_sysfs_early_fini().
1519 * Freeing it here would leave a dangling pointer in the early
1520 * discovery list, causing a use-after-free on driver unbind.
1521 */
1522 if (ip_top->standalone_mode)
1523 return;
1524
1525 adev->discovery.ip_top = NULL;
1526 die_kset = &ip_top->die_kset;
1527 spin_lock(&die_kset->list_lock);
1528 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1529 list_del_init(el);
1530 spin_unlock(&die_kset->list_lock);
1531 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1532 spin_lock(&die_kset->list_lock);
1533 }
1534 spin_unlock(&die_kset->list_lock);
1535 kobject_put(&ip_top->die_kset.kobj);
1536 kobject_put(&ip_top->kobj);
1537 }
1538
1539 /* devcoredump support */
amdgpu_discovery_dump(struct amdgpu_device * adev,struct drm_printer * p)1540 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p)
1541 {
1542 struct ip_discovery_top *ip_top = adev->discovery.ip_top;
1543 struct ip_die_entry *ip_die_entry;
1544 struct list_head *el_die, *el_hw_id, *el_hw_inst;
1545 struct ip_hw_id *hw_id;
1546 struct kset *die_kset;
1547 struct ip_hw_instance *ip_inst;
1548 int i = 0, j;
1549
1550 if (!ip_top)
1551 return;
1552
1553 die_kset = &ip_top->die_kset;
1554
1555 drm_printf(p, "\nHW IP Discovery\n");
1556
1557 spin_lock(&die_kset->list_lock);
1558 list_for_each(el_die, &die_kset->list) {
1559 drm_printf(p, "die %d\n", i++);
1560 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die));
1561
1562 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) {
1563 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id));
1564 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]);
1565
1566 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) {
1567 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst));
1568 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance);
1569 drm_printf(p, "\tmajor %d\n", ip_inst->major);
1570 drm_printf(p, "\tminor %d\n", ip_inst->minor);
1571 drm_printf(p, "\trevision %d\n", ip_inst->revision);
1572 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest);
1573 drm_printf(p, "\tnum_base_addresses %d\n",
1574 ip_inst->num_base_addresses);
1575 for (j = 0; j < ip_inst->num_base_addresses; j++)
1576 drm_printf(p, "\tbase_addr[%d] 0x%08X\n",
1577 j, ip_inst->base_addr[j]);
1578 }
1579 }
1580 }
1581 spin_unlock(&die_kset->list_lock);
1582 }
1583
amdgpu_discovery_sysfs_early_init(struct amdgpu_device * adev,struct pci_dev * pdev)1584 int amdgpu_discovery_sysfs_early_init(struct amdgpu_device *adev, struct pci_dev *pdev)
1585 {
1586 struct ip_discovery_top *ip_top;
1587 struct early_ip_discovery *early_entry, *tmp;
1588 struct kset *die_kset;
1589 uint8_t *discovery_bin;
1590 int res, ii;
1591
1592 if (!adev || !adev->discovery.bin)
1593 return -EINVAL;
1594
1595 if (adev->discovery.ip_top)
1596 return 0;
1597
1598 mutex_lock(&early_ip_discovery_mutex);
1599 list_for_each_entry_safe(early_entry, tmp, &early_ip_discovery_list, list) {
1600 if (early_entry->pdev == pdev) {
1601 adev->discovery.ip_top = early_entry->ip_top;
1602 early_entry->ip_top->adev = adev;
1603 mutex_unlock(&early_ip_discovery_mutex);
1604 return 0;
1605 }
1606 }
1607 mutex_unlock(&early_ip_discovery_mutex);
1608
1609 discovery_bin = adev->discovery.bin;
1610
1611 early_entry = kzalloc_obj(*early_entry);
1612 if (!early_entry)
1613 return -ENOMEM;
1614
1615 ip_top = kzalloc_obj(*ip_top);
1616 if (!ip_top) {
1617 kfree(early_entry);
1618 return -ENOMEM;
1619 }
1620
1621 ip_top->discovery_bin = devm_kmemdup(&pdev->dev, discovery_bin,
1622 DISCOVERY_TMR_SIZE, GFP_KERNEL);
1623 if (!ip_top->discovery_bin) {
1624 kfree(ip_top);
1625 kfree(early_entry);
1626 return -ENOMEM;
1627 }
1628
1629 ip_top->bin_size = DISCOVERY_TMR_SIZE;
1630 ip_top->pdev = pdev;
1631 ip_top->adev = adev;
1632 ip_top->standalone_mode = true;
1633
1634 /* Check if ip_discovery already exists (from previous probe attempt).
1635 * This can happen if the module was unloaded and reloaded but the
1636 * sysfs persisted (tied to PCI device lifetime).
1637 */
1638 if (pdev->dev.kobj.sd) {
1639 struct kernfs_node *existing;
1640
1641 existing = kernfs_find_and_get(pdev->dev.kobj.sd, "ip_discovery");
1642 if (existing) {
1643 kernfs_put(existing);
1644 kfree(ip_top);
1645 kfree(early_entry);
1646 return 0;
1647 }
1648 }
1649
1650 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype,
1651 &pdev->dev.kobj, "ip_discovery");
1652 if (res)
1653 goto err_put_kobj;
1654
1655 adev->discovery.ip_top = ip_top;
1656
1657 die_kset = &ip_top->die_kset;
1658 kobject_set_name(&die_kset->kobj, "%s", "die");
1659 die_kset->kobj.parent = &ip_top->kobj;
1660 die_kset->kobj.ktype = &die_kobj_ktype;
1661 res = kset_register(&ip_top->die_kset);
1662 if (res)
1663 goto err_put_die_kset;
1664
1665 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1666 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1667 ip_hw_instance_attrs[ii] = NULL;
1668
1669 res = amdgpu_discovery_sysfs_recurse(NULL, ip_top);
1670 if (res)
1671 goto err_put_die_kset;
1672
1673 early_entry->pdev = pdev;
1674 early_entry->ip_top = ip_top;
1675 mutex_lock(&early_ip_discovery_mutex);
1676 list_add(&early_entry->list, &early_ip_discovery_list);
1677 mutex_unlock(&early_ip_discovery_mutex);
1678
1679 return 0;
1680
1681 err_put_die_kset:
1682 kobject_put(&ip_top->die_kset.kobj);
1683 err_put_kobj:
1684 kobject_put(&ip_top->kobj);
1685 kfree(early_entry);
1686 adev->discovery.ip_top = NULL;
1687 return res;
1688 }
1689
amdgpu_discovery_sysfs_early_fini(struct pci_dev * pdev)1690 void amdgpu_discovery_sysfs_early_fini(struct pci_dev *pdev)
1691 {
1692 struct early_ip_discovery *entry, *tmp_entry;
1693 struct ip_discovery_top *ip_top = NULL;
1694 struct list_head *el, *tmp;
1695 struct kset *die_kset;
1696
1697 /* Find the entry in our tracking list */
1698 mutex_lock(&early_ip_discovery_mutex);
1699 list_for_each_entry_safe(entry, tmp_entry, &early_ip_discovery_list, list) {
1700 if (entry->pdev == pdev) {
1701 ip_top = entry->ip_top;
1702 list_del(&entry->list);
1703 kfree(entry);
1704 break;
1705 }
1706 }
1707 mutex_unlock(&early_ip_discovery_mutex);
1708
1709 if (!ip_top)
1710 return;
1711
1712 /* Clean up sysfs hierarchy */
1713 die_kset = &ip_top->die_kset;
1714
1715 spin_lock(&die_kset->list_lock);
1716 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1717 list_del_init(el);
1718 spin_unlock(&die_kset->list_lock);
1719 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1720 spin_lock(&die_kset->list_lock);
1721 }
1722 spin_unlock(&die_kset->list_lock);
1723
1724 kobject_put(&ip_top->die_kset.kobj);
1725 kobject_put(&ip_top->kobj);
1726 /* ip_top itself will be freed by kobject_put via ip_disc_release */
1727 }
1728
1729 /* ================================================== */
1730
amdgpu_discovery_reg_base_init(struct amdgpu_device * adev)1731 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1732 {
1733 uint8_t num_base_address, subrev, variant;
1734 struct table_info *info;
1735 struct ip_discovery_header *ihdr;
1736 struct die_header *dhdr;
1737 uint8_t *discovery_bin;
1738 struct ip_v4 *ip;
1739 uint16_t die_offset;
1740 uint16_t ip_offset;
1741 uint16_t num_dies;
1742 uint32_t wafl_ver;
1743 uint16_t num_ips;
1744 uint16_t hw_id;
1745 uint8_t inst;
1746 int hw_ip;
1747 int i, j, k;
1748 int r;
1749
1750 r = amdgpu_discovery_init(adev);
1751 if (r)
1752 return r;
1753
1754 amdgpu_discovery_sysfs_early_init(adev, adev->pdev);
1755
1756 discovery_bin = adev->discovery.bin;
1757 wafl_ver = 0;
1758 adev->gfx.xcc_mask = 0;
1759 adev->sdma.sdma_mask = 0;
1760 adev->vcn.inst_mask = 0;
1761 adev->jpeg.inst_mask = 0;
1762 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY);
1763 if (r)
1764 return r;
1765 ihdr = (struct ip_discovery_header
1766 *)(discovery_bin +
1767 le16_to_cpu(info->offset));
1768 num_dies = le16_to_cpu(ihdr->num_dies);
1769
1770 DRM_DEBUG("number of dies: %d\n", num_dies);
1771
1772 for (i = 0; i < num_dies; i++) {
1773 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1774 dhdr = (struct die_header *)(discovery_bin + die_offset);
1775 num_ips = le16_to_cpu(dhdr->num_ips);
1776 ip_offset = die_offset + sizeof(*dhdr);
1777
1778 if (le16_to_cpu(dhdr->die_id) != i) {
1779 DRM_ERROR("invalid die id %d, expected %d\n",
1780 le16_to_cpu(dhdr->die_id), i);
1781 return -EINVAL;
1782 }
1783
1784 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1785 le16_to_cpu(dhdr->die_id), num_ips);
1786
1787 for (j = 0; j < num_ips; j++) {
1788 ip = (struct ip_v4 *)(discovery_bin + ip_offset);
1789
1790 inst = ip->instance_number;
1791 hw_id = le16_to_cpu(ip->hw_id);
1792 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
1793 goto next_ip;
1794
1795 num_base_address = ip->num_base_address;
1796
1797 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1798 hw_id_names[le16_to_cpu(ip->hw_id)],
1799 le16_to_cpu(ip->hw_id),
1800 ip->instance_number,
1801 ip->major, ip->minor,
1802 ip->revision);
1803
1804 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1805 /* Bit [5:0]: original revision value
1806 * Bit [7:6]: en/decode capability:
1807 * 0b00 : VCN function normally
1808 * 0b10 : encode is disabled
1809 * 0b01 : decode is disabled
1810 */
1811 if (adev->vcn.num_vcn_inst <
1812 AMDGPU_MAX_VCN_INSTANCES) {
1813 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
1814 ip->revision & 0xc0;
1815 adev->vcn.num_vcn_inst++;
1816 adev->vcn.inst_mask |=
1817 (1U << ip->instance_number);
1818 adev->jpeg.inst_mask |=
1819 (1U << ip->instance_number);
1820 } else {
1821 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1822 adev->vcn.num_vcn_inst + 1,
1823 AMDGPU_MAX_VCN_INSTANCES);
1824 }
1825 ip->revision &= ~0xc0;
1826 }
1827 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1828 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1829 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1830 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1831 if (adev->sdma.num_instances <
1832 AMDGPU_MAX_SDMA_INSTANCES) {
1833 adev->sdma.num_instances++;
1834 adev->sdma.sdma_mask |=
1835 (1U << ip->instance_number);
1836 } else {
1837 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1838 adev->sdma.num_instances + 1,
1839 AMDGPU_MAX_SDMA_INSTANCES);
1840 }
1841 }
1842
1843 if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1844 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1845 adev->vpe.num_instances++;
1846 else
1847 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1848 adev->vpe.num_instances + 1,
1849 AMDGPU_MAX_VPE_INSTANCES);
1850 }
1851
1852 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1853 adev->gmc.num_umc++;
1854 adev->umc.node_inst_num++;
1855 }
1856
1857 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1858 adev->gfx.xcc_mask |=
1859 (1U << ip->instance_number);
1860
1861 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID)
1862 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor,
1863 ip->revision, 0, 0);
1864
1865 for (k = 0; k < num_base_address; k++) {
1866 /*
1867 * convert the endianness of base addresses in place,
1868 * so that we don't need to convert them when accessing adev->reg_offset.
1869 */
1870 if (ihdr->base_addr_64_bit)
1871 /* Truncate the 64bit base address from ip discovery
1872 * and only store lower 32bit ip base in reg_offset[].
1873 * Bits > 32 follows ASIC specific format, thus just
1874 * discard them and handle it within specific ASIC.
1875 * By this way reg_offset[] and related helpers can
1876 * stay unchanged.
1877 * The base address is in dwords, thus clear the
1878 * highest 2 bits to store.
1879 */
1880 ip->base_address[k] =
1881 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1882 else
1883 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1884 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1885 }
1886
1887 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1888 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1889 hw_id_map[hw_ip] != 0) {
1890 DRM_DEBUG("set register base offset for %s\n",
1891 hw_id_names[le16_to_cpu(ip->hw_id)]);
1892 adev->reg_offset[hw_ip][ip->instance_number] =
1893 ip->base_address;
1894 /* Instance support is somewhat inconsistent.
1895 * SDMA is a good example. Sienna cichlid has 4 total
1896 * SDMA instances, each enumerated separately (HWIDs
1897 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1898 * but they are enumerated as multiple instances of the
1899 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1900 * example. On most chips there are multiple instances
1901 * with the same HWID.
1902 */
1903
1904 if (ihdr->version < 3) {
1905 subrev = 0;
1906 variant = 0;
1907 } else {
1908 subrev = ip->sub_revision;
1909 variant = ip->variant;
1910 }
1911
1912 adev->ip_versions[hw_ip]
1913 [ip->instance_number] =
1914 IP_VERSION_FULL(ip->major,
1915 ip->minor,
1916 ip->revision,
1917 variant,
1918 subrev);
1919 }
1920 }
1921
1922 next_ip:
1923 if (ihdr->base_addr_64_bit)
1924 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1925 else
1926 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1927 }
1928 }
1929
1930 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0])
1931 adev->ip_versions[XGMI_HWIP][0] = wafl_ver;
1932
1933 return 0;
1934 }
1935
amdgpu_discovery_harvest_ip(struct amdgpu_device * adev)1936 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1937 {
1938 uint8_t *discovery_bin = adev->discovery.bin;
1939 struct ip_discovery_header *ihdr;
1940 struct table_info *info;
1941 int vcn_harvest_count = 0;
1942 int umc_harvest_count = 0;
1943 uint16_t ihdr_ver;
1944
1945 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY))
1946 return;
1947 ihdr = (struct ip_discovery_header *)(discovery_bin +
1948 le16_to_cpu(info->offset));
1949 ihdr_ver = le16_to_cpu(ihdr->version);
1950 /*
1951 * Harvest table does not fit Navi1x and legacy GPUs,
1952 * so read harvest bit per IP data structure to set
1953 * harvest configuration.
1954 */
1955 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1956 ihdr_ver <= 2) {
1957 if ((adev->pdev->device == 0x731E &&
1958 (adev->pdev->revision == 0xC6 ||
1959 adev->pdev->revision == 0xC7)) ||
1960 (adev->pdev->device == 0x7340 &&
1961 adev->pdev->revision == 0xC9) ||
1962 (adev->pdev->device == 0x7360 &&
1963 adev->pdev->revision == 0xC7))
1964 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1965 &vcn_harvest_count);
1966 } else {
1967 amdgpu_discovery_read_from_harvest_table(adev,
1968 &vcn_harvest_count,
1969 &umc_harvest_count);
1970 }
1971
1972 amdgpu_discovery_harvest_config_quirk(adev);
1973
1974 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1975 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1976 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1977 }
1978
1979 if (umc_harvest_count < adev->gmc.num_umc) {
1980 adev->gmc.num_umc -= umc_harvest_count;
1981 }
1982 }
1983
1984 union gc_info {
1985 struct gc_info_v1_0 v1;
1986 struct gc_info_v1_1 v1_1;
1987 struct gc_info_v1_2 v1_2;
1988 struct gc_info_v1_3 v1_3;
1989 struct gc_info_v2_0 v2;
1990 struct gc_info_v2_1 v2_1;
1991 };
1992
amdgpu_discovery_get_gfx_info(struct amdgpu_device * adev)1993 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1994 {
1995 uint8_t *discovery_bin = adev->discovery.bin;
1996 struct table_info *info;
1997 union gc_info *gc_info;
1998 u16 offset;
1999
2000 if (!discovery_bin) {
2001 DRM_ERROR("ip discovery uninitialized\n");
2002 return -EINVAL;
2003 }
2004
2005 if (amdgpu_discovery_get_table_info(adev, &info, GC))
2006 return -EINVAL;
2007 offset = le16_to_cpu(info->offset);
2008
2009 if (!offset)
2010 return 0;
2011
2012 gc_info = (union gc_info *)(discovery_bin + offset);
2013
2014 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
2015 case 1:
2016 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
2017 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
2018 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
2019 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2020 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
2021 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
2022 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
2023 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
2024 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
2025 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
2026 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
2027 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
2028 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
2029 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
2030 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
2031 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
2032 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
2033 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
2034 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
2035 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
2036 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
2037 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
2038 }
2039 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
2040 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
2041 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
2042 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
2043 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
2044 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
2045 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
2046 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
2047 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
2048 }
2049 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
2050 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
2051 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
2052 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
2053 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
2054 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
2055 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
2056 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
2057 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
2058 }
2059 break;
2060 case 2:
2061 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
2062 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
2063 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2064 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
2065 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
2066 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
2067 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
2068 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
2069 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
2070 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
2071 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
2072 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
2073 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
2074 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
2075 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
2076 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
2077 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
2078 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
2079 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
2080 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
2081 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
2082 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
2083 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
2084 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
2085 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
2086 }
2087 break;
2088 default:
2089 dev_err(adev->dev,
2090 "Unhandled GC info table %d.%d\n",
2091 le16_to_cpu(gc_info->v1.header.version_major),
2092 le16_to_cpu(gc_info->v1.header.version_minor));
2093 return -EINVAL;
2094 }
2095 return 0;
2096 }
2097
2098 union mall_info {
2099 struct mall_info_v1_0 v1;
2100 struct mall_info_v2_0 v2;
2101 };
2102
amdgpu_discovery_get_mall_info(struct amdgpu_device * adev)2103 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
2104 {
2105 uint8_t *discovery_bin = adev->discovery.bin;
2106 struct table_info *info;
2107 union mall_info *mall_info;
2108 u32 u, mall_size_per_umc, m_s_present, half_use;
2109 u64 mall_size;
2110 u16 offset;
2111
2112 if (!discovery_bin) {
2113 DRM_ERROR("ip discovery uninitialized\n");
2114 return -EINVAL;
2115 }
2116
2117 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO))
2118 return -EINVAL;
2119 offset = le16_to_cpu(info->offset);
2120
2121 if (!offset)
2122 return 0;
2123
2124 mall_info = (union mall_info *)(discovery_bin + offset);
2125
2126 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
2127 case 1:
2128 mall_size = 0;
2129 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
2130 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
2131 half_use = le32_to_cpu(mall_info->v1.m_half_use);
2132 for (u = 0; u < adev->gmc.num_umc; u++) {
2133 if (m_s_present & (1 << u))
2134 mall_size += mall_size_per_umc * 2;
2135 else if (half_use & (1 << u))
2136 mall_size += mall_size_per_umc / 2;
2137 else
2138 mall_size += mall_size_per_umc;
2139 }
2140 adev->gmc.mall_size = mall_size;
2141 adev->gmc.m_half_use = half_use;
2142 break;
2143 case 2:
2144 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
2145 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
2146 break;
2147 default:
2148 dev_err(adev->dev,
2149 "Unhandled MALL info table %d.%d\n",
2150 le16_to_cpu(mall_info->v1.header.version_major),
2151 le16_to_cpu(mall_info->v1.header.version_minor));
2152 return -EINVAL;
2153 }
2154 return 0;
2155 }
2156
2157 union vcn_info {
2158 struct vcn_info_v1_0 v1;
2159 };
2160
amdgpu_discovery_get_vcn_info(struct amdgpu_device * adev)2161 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
2162 {
2163 uint8_t *discovery_bin = adev->discovery.bin;
2164 struct table_info *info;
2165 union vcn_info *vcn_info;
2166 u16 offset;
2167 int v;
2168
2169 if (!discovery_bin) {
2170 DRM_ERROR("ip discovery uninitialized\n");
2171 return -EINVAL;
2172 }
2173
2174 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2175 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
2176 * but that may change in the future with new GPUs so keep this
2177 * check for defensive purposes.
2178 */
2179 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
2180 dev_err(adev->dev, "invalid vcn instances\n");
2181 return -EINVAL;
2182 }
2183
2184 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO))
2185 return -EINVAL;
2186 offset = le16_to_cpu(info->offset);
2187
2188 if (!offset)
2189 return 0;
2190
2191 vcn_info = (union vcn_info *)(discovery_bin + offset);
2192
2193 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
2194 case 1:
2195 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
2196 * so this won't overflow.
2197 */
2198 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
2199 adev->vcn.inst[v].vcn_codec_disable_mask =
2200 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
2201 }
2202 break;
2203 default:
2204 dev_err(adev->dev,
2205 "Unhandled VCN info table %d.%d\n",
2206 le16_to_cpu(vcn_info->v1.header.version_major),
2207 le16_to_cpu(vcn_info->v1.header.version_minor));
2208 return -EINVAL;
2209 }
2210 return 0;
2211 }
2212
2213 union nps_info {
2214 struct nps_info_v1_0 v1;
2215 };
2216
amdgpu_discovery_refresh_nps_info(struct amdgpu_device * adev,union nps_info * nps_data)2217 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,
2218 union nps_info *nps_data)
2219 {
2220 uint64_t vram_size, pos, offset;
2221 struct nps_info_header *nhdr;
2222 struct binary_header bhdr;
2223 struct binary_header_v2 bhdrv2;
2224 uint16_t checksum;
2225
2226 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
2227 pos = vram_size - DISCOVERY_TMR_OFFSET;
2228 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
2229
2230 switch (bhdr.version_major) {
2231 case 2:
2232 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false);
2233 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset);
2234 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum);
2235 break;
2236 case 1:
2237 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);
2238 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);
2239 break;
2240 default:
2241 return -EINVAL;
2242 }
2243
2244 amdgpu_device_vram_access(adev, (pos + offset), nps_data,
2245 sizeof(*nps_data), false);
2246
2247 nhdr = (struct nps_info_header *)(nps_data);
2248 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data,
2249 le32_to_cpu(nhdr->size_bytes),
2250 checksum)) {
2251 dev_err(adev->dev, "nps data refresh, checksum mismatch\n");
2252 return -EINVAL;
2253 }
2254
2255 return 0;
2256 }
2257
amdgpu_discovery_get_nps_info(struct amdgpu_device * adev,uint32_t * nps_type,struct amdgpu_gmc_memrange * ranges,int * range_cnt,bool refresh)2258 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
2259 uint32_t *nps_type,
2260 struct amdgpu_gmc_memrange *ranges,
2261 int *range_cnt, bool refresh)
2262 {
2263 uint8_t *discovery_bin = adev->discovery.bin;
2264 struct table_info *info;
2265 union nps_info *nps_info;
2266 union nps_info nps_data;
2267 u16 offset;
2268 int i, r;
2269
2270 if (!nps_type || !range_cnt || !ranges)
2271 return -EINVAL;
2272
2273 if (refresh) {
2274 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data);
2275 if (r)
2276 return r;
2277 nps_info = &nps_data;
2278 } else {
2279 if (!discovery_bin) {
2280 dev_err(adev->dev,
2281 "fetch mem range failed, ip discovery uninitialized\n");
2282 return -EINVAL;
2283 }
2284
2285 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO))
2286 return -EINVAL;
2287 offset = le16_to_cpu(info->offset);
2288
2289 if (!offset)
2290 return -ENOENT;
2291
2292 /* If verification fails, return as if NPS table doesn't exist */
2293 if (amdgpu_discovery_verify_npsinfo(adev, info))
2294 return -ENOENT;
2295
2296 nps_info = (union nps_info *)(discovery_bin + offset);
2297 }
2298
2299 switch (le16_to_cpu(nps_info->v1.header.version_major)) {
2300 case 1:
2301 *nps_type = nps_info->v1.nps_type;
2302 if (*range_cnt < nps_info->v1.count) {
2303 dev_dbg(adev->dev,
2304 "not enough space for nps ranges: %d < %d\n",
2305 *range_cnt, nps_info->v1.count);
2306 return -ENOSPC;
2307 }
2308 *range_cnt = nps_info->v1.count;
2309 for (i = 0; i < *range_cnt; i++) {
2310 ranges[i].base_address =
2311 nps_info->v1.instance_info[i].base_address;
2312 ranges[i].limit_address =
2313 nps_info->v1.instance_info[i].limit_address;
2314 ranges[i].nid_mask = -1;
2315 ranges[i].flags = 0;
2316 }
2317 break;
2318 default:
2319 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
2320 le16_to_cpu(nps_info->v1.header.version_major),
2321 le16_to_cpu(nps_info->v1.header.version_minor));
2322 return -EINVAL;
2323 }
2324
2325 return 0;
2326 }
2327
amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device * adev)2328 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
2329 {
2330 /* what IP to use for this? */
2331 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2332 case IP_VERSION(9, 0, 1):
2333 case IP_VERSION(9, 1, 0):
2334 case IP_VERSION(9, 2, 1):
2335 case IP_VERSION(9, 2, 2):
2336 case IP_VERSION(9, 3, 0):
2337 case IP_VERSION(9, 4, 0):
2338 case IP_VERSION(9, 4, 1):
2339 case IP_VERSION(9, 4, 2):
2340 case IP_VERSION(9, 4, 3):
2341 case IP_VERSION(9, 4, 4):
2342 case IP_VERSION(9, 5, 0):
2343 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
2344 break;
2345 case IP_VERSION(10, 1, 10):
2346 case IP_VERSION(10, 1, 1):
2347 case IP_VERSION(10, 1, 2):
2348 case IP_VERSION(10, 1, 3):
2349 case IP_VERSION(10, 1, 4):
2350 case IP_VERSION(10, 3, 0):
2351 case IP_VERSION(10, 3, 1):
2352 case IP_VERSION(10, 3, 2):
2353 case IP_VERSION(10, 3, 3):
2354 case IP_VERSION(10, 3, 4):
2355 case IP_VERSION(10, 3, 5):
2356 case IP_VERSION(10, 3, 6):
2357 case IP_VERSION(10, 3, 7):
2358 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
2359 break;
2360 case IP_VERSION(11, 0, 0):
2361 case IP_VERSION(11, 0, 1):
2362 case IP_VERSION(11, 0, 2):
2363 case IP_VERSION(11, 0, 3):
2364 case IP_VERSION(11, 0, 4):
2365 case IP_VERSION(11, 5, 0):
2366 case IP_VERSION(11, 5, 1):
2367 case IP_VERSION(11, 5, 2):
2368 case IP_VERSION(11, 5, 3):
2369 case IP_VERSION(11, 5, 4):
2370 case IP_VERSION(11, 5, 6):
2371 case IP_VERSION(11, 7, 0):
2372 case IP_VERSION(11, 7, 1):
2373 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
2374 break;
2375 case IP_VERSION(12, 0, 0):
2376 case IP_VERSION(12, 0, 1):
2377 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
2378 break;
2379 case IP_VERSION(12, 1, 0):
2380 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block);
2381 break;
2382 default:
2383 dev_err(adev->dev,
2384 "Failed to add common ip block(GC_HWIP:0x%x)\n",
2385 amdgpu_ip_version(adev, GC_HWIP, 0));
2386 return -EINVAL;
2387 }
2388 return 0;
2389 }
2390
amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device * adev)2391 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
2392 {
2393 /* use GC or MMHUB IP version */
2394 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2395 case IP_VERSION(9, 0, 1):
2396 case IP_VERSION(9, 1, 0):
2397 case IP_VERSION(9, 2, 1):
2398 case IP_VERSION(9, 2, 2):
2399 case IP_VERSION(9, 3, 0):
2400 case IP_VERSION(9, 4, 0):
2401 case IP_VERSION(9, 4, 1):
2402 case IP_VERSION(9, 4, 2):
2403 case IP_VERSION(9, 4, 3):
2404 case IP_VERSION(9, 4, 4):
2405 case IP_VERSION(9, 5, 0):
2406 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2407 break;
2408 case IP_VERSION(10, 1, 10):
2409 case IP_VERSION(10, 1, 1):
2410 case IP_VERSION(10, 1, 2):
2411 case IP_VERSION(10, 1, 3):
2412 case IP_VERSION(10, 1, 4):
2413 case IP_VERSION(10, 3, 0):
2414 case IP_VERSION(10, 3, 1):
2415 case IP_VERSION(10, 3, 2):
2416 case IP_VERSION(10, 3, 3):
2417 case IP_VERSION(10, 3, 4):
2418 case IP_VERSION(10, 3, 5):
2419 case IP_VERSION(10, 3, 6):
2420 case IP_VERSION(10, 3, 7):
2421 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
2422 break;
2423 case IP_VERSION(11, 0, 0):
2424 case IP_VERSION(11, 0, 1):
2425 case IP_VERSION(11, 0, 2):
2426 case IP_VERSION(11, 0, 3):
2427 case IP_VERSION(11, 0, 4):
2428 case IP_VERSION(11, 5, 0):
2429 case IP_VERSION(11, 5, 1):
2430 case IP_VERSION(11, 5, 2):
2431 case IP_VERSION(11, 5, 3):
2432 case IP_VERSION(11, 5, 4):
2433 case IP_VERSION(11, 5, 6):
2434 case IP_VERSION(11, 7, 0):
2435 case IP_VERSION(11, 7, 1):
2436 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
2437 break;
2438 case IP_VERSION(12, 0, 0):
2439 case IP_VERSION(12, 0, 1):
2440 case IP_VERSION(12, 1, 0):
2441 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
2442 break;
2443 default:
2444 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
2445 amdgpu_ip_version(adev, GC_HWIP, 0));
2446 return -EINVAL;
2447 }
2448 return 0;
2449 }
2450
amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device * adev)2451 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
2452 {
2453 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
2454 case IP_VERSION(4, 0, 0):
2455 case IP_VERSION(4, 0, 1):
2456 case IP_VERSION(4, 1, 0):
2457 case IP_VERSION(4, 1, 1):
2458 case IP_VERSION(4, 3, 0):
2459 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
2460 break;
2461 case IP_VERSION(4, 2, 0):
2462 case IP_VERSION(4, 2, 1):
2463 case IP_VERSION(4, 4, 0):
2464 case IP_VERSION(4, 4, 2):
2465 case IP_VERSION(4, 4, 5):
2466 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
2467 break;
2468 case IP_VERSION(5, 0, 0):
2469 case IP_VERSION(5, 0, 1):
2470 case IP_VERSION(5, 0, 2):
2471 case IP_VERSION(5, 0, 3):
2472 case IP_VERSION(5, 2, 0):
2473 case IP_VERSION(5, 2, 1):
2474 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
2475 break;
2476 case IP_VERSION(6, 0, 0):
2477 case IP_VERSION(6, 0, 1):
2478 case IP_VERSION(6, 0, 2):
2479 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
2480 break;
2481 case IP_VERSION(6, 1, 0):
2482 case IP_VERSION(6, 1, 1):
2483 case IP_VERSION(6, 4, 0):
2484 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
2485 break;
2486 case IP_VERSION(7, 0, 0):
2487 case IP_VERSION(7, 1, 0):
2488 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
2489 break;
2490 default:
2491 dev_err(adev->dev,
2492 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
2493 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
2494 return -EINVAL;
2495 }
2496 return 0;
2497 }
2498
amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device * adev)2499 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
2500 {
2501 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2502 case IP_VERSION(9, 0, 0):
2503 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
2504 break;
2505 case IP_VERSION(10, 0, 0):
2506 case IP_VERSION(10, 0, 1):
2507 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
2508 break;
2509 case IP_VERSION(11, 0, 0):
2510 case IP_VERSION(11, 0, 2):
2511 case IP_VERSION(11, 0, 4):
2512 case IP_VERSION(11, 0, 5):
2513 case IP_VERSION(11, 0, 9):
2514 case IP_VERSION(11, 0, 7):
2515 case IP_VERSION(11, 0, 11):
2516 case IP_VERSION(11, 0, 12):
2517 case IP_VERSION(11, 0, 13):
2518 case IP_VERSION(11, 5, 0):
2519 case IP_VERSION(11, 5, 2):
2520 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
2521 break;
2522 case IP_VERSION(11, 0, 8):
2523 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
2524 break;
2525 case IP_VERSION(11, 0, 3):
2526 case IP_VERSION(12, 0, 1):
2527 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
2528 break;
2529 case IP_VERSION(13, 0, 0):
2530 case IP_VERSION(13, 0, 1):
2531 case IP_VERSION(13, 0, 2):
2532 case IP_VERSION(13, 0, 3):
2533 case IP_VERSION(13, 0, 5):
2534 case IP_VERSION(13, 0, 6):
2535 case IP_VERSION(13, 0, 7):
2536 case IP_VERSION(13, 0, 8):
2537 case IP_VERSION(13, 0, 10):
2538 case IP_VERSION(13, 0, 11):
2539 case IP_VERSION(13, 0, 12):
2540 case IP_VERSION(13, 0, 14):
2541 case IP_VERSION(13, 0, 15):
2542 case IP_VERSION(14, 0, 0):
2543 case IP_VERSION(14, 0, 1):
2544 case IP_VERSION(14, 0, 4):
2545 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
2546 break;
2547 case IP_VERSION(13, 0, 4):
2548 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
2549 break;
2550 case IP_VERSION(14, 0, 2):
2551 case IP_VERSION(14, 0, 3):
2552 case IP_VERSION(14, 0, 5):
2553 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2554 break;
2555 case IP_VERSION(15, 0, 0):
2556 case IP_VERSION(15, 0, 5):
2557 case IP_VERSION(15, 0, 9):
2558 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
2559 break;
2560 case IP_VERSION(15, 0, 8):
2561 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block);
2562 break;
2563 default:
2564 dev_err(adev->dev,
2565 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
2566 amdgpu_ip_version(adev, MP0_HWIP, 0));
2567 return -EINVAL;
2568 }
2569 return 0;
2570 }
2571
amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device * adev)2572 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
2573 {
2574 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2575 case IP_VERSION(9, 0, 0):
2576 case IP_VERSION(10, 0, 0):
2577 case IP_VERSION(10, 0, 1):
2578 case IP_VERSION(11, 0, 2):
2579 if (adev->asic_type == CHIP_ARCTURUS)
2580 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2581 else
2582 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2583 break;
2584 case IP_VERSION(11, 0, 0):
2585 case IP_VERSION(11, 0, 5):
2586 case IP_VERSION(11, 0, 9):
2587 case IP_VERSION(11, 0, 7):
2588 case IP_VERSION(11, 0, 11):
2589 case IP_VERSION(11, 0, 12):
2590 case IP_VERSION(11, 0, 13):
2591 case IP_VERSION(11, 5, 0):
2592 case IP_VERSION(11, 5, 2):
2593 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2594 break;
2595 case IP_VERSION(11, 0, 8):
2596 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
2597 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2598 break;
2599 case IP_VERSION(12, 0, 0):
2600 case IP_VERSION(12, 0, 1):
2601 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2602 break;
2603 case IP_VERSION(13, 0, 0):
2604 case IP_VERSION(13, 0, 1):
2605 case IP_VERSION(13, 0, 2):
2606 case IP_VERSION(13, 0, 3):
2607 case IP_VERSION(13, 0, 4):
2608 case IP_VERSION(13, 0, 5):
2609 case IP_VERSION(13, 0, 6):
2610 case IP_VERSION(13, 0, 7):
2611 case IP_VERSION(13, 0, 8):
2612 case IP_VERSION(13, 0, 10):
2613 case IP_VERSION(13, 0, 11):
2614 case IP_VERSION(13, 0, 14):
2615 case IP_VERSION(13, 0, 12):
2616 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2617 break;
2618 case IP_VERSION(14, 0, 0):
2619 case IP_VERSION(14, 0, 1):
2620 case IP_VERSION(14, 0, 2):
2621 case IP_VERSION(14, 0, 3):
2622 case IP_VERSION(14, 0, 4):
2623 case IP_VERSION(14, 0, 5):
2624 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2625 break;
2626 case IP_VERSION(15, 0, 0):
2627 case IP_VERSION(15, 0, 5):
2628 case IP_VERSION(15, 0, 8):
2629 case IP_VERSION(15, 0, 9):
2630 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block);
2631 break;
2632 default:
2633 dev_err(adev->dev,
2634 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2635 amdgpu_ip_version(adev, MP1_HWIP, 0));
2636 return -EINVAL;
2637 }
2638 return 0;
2639 }
2640
2641 #if defined(CONFIG_DRM_AMD_DC)
amdgpu_discovery_set_sriov_display(struct amdgpu_device * adev)2642 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2643 {
2644 amdgpu_device_set_sriov_virtual_display(adev);
2645 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2646 }
2647 #endif
2648
amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device * adev)2649 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2650 {
2651 if (adev->enable_virtual_display) {
2652 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2653 return 0;
2654 }
2655
2656 if (!amdgpu_device_has_dc_support(adev))
2657 return 0;
2658
2659 #if defined(CONFIG_DRM_AMD_DC)
2660 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2661 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2662 case IP_VERSION(1, 0, 0):
2663 case IP_VERSION(1, 0, 1):
2664 case IP_VERSION(2, 0, 2):
2665 case IP_VERSION(2, 0, 0):
2666 case IP_VERSION(2, 0, 3):
2667 case IP_VERSION(2, 1, 0):
2668 case IP_VERSION(3, 0, 0):
2669 case IP_VERSION(3, 0, 2):
2670 case IP_VERSION(3, 0, 3):
2671 case IP_VERSION(3, 0, 1):
2672 case IP_VERSION(3, 1, 2):
2673 case IP_VERSION(3, 1, 3):
2674 case IP_VERSION(3, 1, 4):
2675 case IP_VERSION(3, 1, 5):
2676 case IP_VERSION(3, 1, 6):
2677 case IP_VERSION(3, 2, 0):
2678 case IP_VERSION(3, 2, 1):
2679 case IP_VERSION(3, 5, 0):
2680 case IP_VERSION(3, 5, 1):
2681 case IP_VERSION(3, 6, 0):
2682 case IP_VERSION(4, 1, 0):
2683 case IP_VERSION(4, 2, 0):
2684 case IP_VERSION(4, 2, 1):
2685 case IP_VERSION(6, 0, 0):
2686 /* TODO: Fix IP version. DC code expects version 4.0.1 */
2687 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2688 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2689
2690 if (amdgpu_sriov_vf(adev))
2691 amdgpu_discovery_set_sriov_display(adev);
2692 else
2693 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2694 break;
2695 default:
2696 dev_err(adev->dev,
2697 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2698 amdgpu_ip_version(adev, DCE_HWIP, 0));
2699 return -EINVAL;
2700 }
2701 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2702 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2703 case IP_VERSION(12, 0, 0):
2704 case IP_VERSION(12, 0, 1):
2705 case IP_VERSION(12, 1, 0):
2706 if (amdgpu_sriov_vf(adev))
2707 amdgpu_discovery_set_sriov_display(adev);
2708 else
2709 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2710 break;
2711 default:
2712 dev_err(adev->dev,
2713 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2714 amdgpu_ip_version(adev, DCI_HWIP, 0));
2715 return -EINVAL;
2716 }
2717 }
2718 #endif
2719 return 0;
2720 }
2721
amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device * adev)2722 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2723 {
2724 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2725 case IP_VERSION(9, 0, 1):
2726 case IP_VERSION(9, 1, 0):
2727 case IP_VERSION(9, 2, 1):
2728 case IP_VERSION(9, 2, 2):
2729 case IP_VERSION(9, 3, 0):
2730 case IP_VERSION(9, 4, 0):
2731 case IP_VERSION(9, 4, 1):
2732 case IP_VERSION(9, 4, 2):
2733 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2734 break;
2735 case IP_VERSION(9, 4, 3):
2736 case IP_VERSION(9, 4, 4):
2737 case IP_VERSION(9, 5, 0):
2738 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2739 break;
2740 case IP_VERSION(10, 1, 10):
2741 case IP_VERSION(10, 1, 2):
2742 case IP_VERSION(10, 1, 1):
2743 case IP_VERSION(10, 1, 3):
2744 case IP_VERSION(10, 1, 4):
2745 case IP_VERSION(10, 3, 0):
2746 case IP_VERSION(10, 3, 2):
2747 case IP_VERSION(10, 3, 1):
2748 case IP_VERSION(10, 3, 4):
2749 case IP_VERSION(10, 3, 5):
2750 case IP_VERSION(10, 3, 6):
2751 case IP_VERSION(10, 3, 3):
2752 case IP_VERSION(10, 3, 7):
2753 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2754 break;
2755 case IP_VERSION(11, 0, 0):
2756 case IP_VERSION(11, 0, 1):
2757 case IP_VERSION(11, 0, 2):
2758 case IP_VERSION(11, 0, 3):
2759 case IP_VERSION(11, 0, 4):
2760 case IP_VERSION(11, 5, 0):
2761 case IP_VERSION(11, 5, 1):
2762 case IP_VERSION(11, 5, 2):
2763 case IP_VERSION(11, 5, 3):
2764 case IP_VERSION(11, 5, 4):
2765 case IP_VERSION(11, 5, 6):
2766 case IP_VERSION(11, 7, 0):
2767 case IP_VERSION(11, 7, 1):
2768 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2769 break;
2770 case IP_VERSION(12, 0, 0):
2771 case IP_VERSION(12, 0, 1):
2772 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2773 break;
2774 case IP_VERSION(12, 1, 0):
2775 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block);
2776 break;
2777 default:
2778 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2779 amdgpu_ip_version(adev, GC_HWIP, 0));
2780 return -EINVAL;
2781 }
2782 return 0;
2783 }
2784
amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device * adev)2785 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2786 {
2787 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2788 case IP_VERSION(4, 0, 0):
2789 case IP_VERSION(4, 0, 1):
2790 case IP_VERSION(4, 1, 0):
2791 case IP_VERSION(4, 1, 1):
2792 case IP_VERSION(4, 1, 2):
2793 case IP_VERSION(4, 2, 0):
2794 case IP_VERSION(4, 2, 2):
2795 case IP_VERSION(4, 4, 0):
2796 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2797 break;
2798 case IP_VERSION(4, 4, 2):
2799 case IP_VERSION(4, 4, 5):
2800 case IP_VERSION(4, 4, 4):
2801 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2802 break;
2803 case IP_VERSION(5, 0, 0):
2804 case IP_VERSION(5, 0, 1):
2805 case IP_VERSION(5, 0, 2):
2806 case IP_VERSION(5, 0, 5):
2807 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2808 break;
2809 case IP_VERSION(5, 2, 0):
2810 case IP_VERSION(5, 2, 2):
2811 case IP_VERSION(5, 2, 4):
2812 case IP_VERSION(5, 2, 5):
2813 case IP_VERSION(5, 2, 6):
2814 case IP_VERSION(5, 2, 3):
2815 case IP_VERSION(5, 2, 1):
2816 case IP_VERSION(5, 2, 7):
2817 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2818 break;
2819 case IP_VERSION(6, 0, 0):
2820 case IP_VERSION(6, 0, 1):
2821 case IP_VERSION(6, 0, 2):
2822 case IP_VERSION(6, 0, 3):
2823 case IP_VERSION(6, 1, 0):
2824 case IP_VERSION(6, 1, 1):
2825 case IP_VERSION(6, 1, 2):
2826 case IP_VERSION(6, 1, 3):
2827 case IP_VERSION(6, 1, 4):
2828 case IP_VERSION(6, 4, 0):
2829 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2830 break;
2831 case IP_VERSION(7, 0, 0):
2832 case IP_VERSION(7, 0, 1):
2833 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2834 break;
2835 case IP_VERSION(7, 1, 0):
2836 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block);
2837 break;
2838 default:
2839 dev_err(adev->dev,
2840 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2841 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2842 return -EINVAL;
2843 }
2844
2845 return 0;
2846 }
2847
amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device * adev)2848 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
2849 {
2850 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2851 case IP_VERSION(13, 0, 6):
2852 case IP_VERSION(13, 0, 12):
2853 case IP_VERSION(13, 0, 14):
2854 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
2855 break;
2856 default:
2857 break;
2858 }
2859 return 0;
2860 }
2861
amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device * adev)2862 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2863 {
2864 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2865 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2866 case IP_VERSION(7, 0, 0):
2867 case IP_VERSION(7, 2, 0):
2868 /* UVD is not supported on vega20 SR-IOV */
2869 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2870 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2871 break;
2872 default:
2873 dev_err(adev->dev,
2874 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2875 amdgpu_ip_version(adev, UVD_HWIP, 0));
2876 return -EINVAL;
2877 }
2878 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2879 case IP_VERSION(4, 0, 0):
2880 case IP_VERSION(4, 1, 0):
2881 /* VCE is not supported on vega20 SR-IOV */
2882 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2883 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2884 break;
2885 default:
2886 dev_err(adev->dev,
2887 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2888 amdgpu_ip_version(adev, VCE_HWIP, 0));
2889 return -EINVAL;
2890 }
2891 } else {
2892 uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0);
2893
2894 /* no VCN discovered; nothing to add */
2895 if (!vcn_version)
2896 return 0;
2897 switch (vcn_version) {
2898 case IP_VERSION(1, 0, 0):
2899 case IP_VERSION(1, 0, 1):
2900 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2901 break;
2902 case IP_VERSION(2, 0, 0):
2903 case IP_VERSION(2, 0, 2):
2904 case IP_VERSION(2, 2, 0):
2905 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2906 if (!amdgpu_sriov_vf(adev))
2907 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2908 break;
2909 case IP_VERSION(2, 0, 3):
2910 break;
2911 case IP_VERSION(2, 5, 0):
2912 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2913 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2914 break;
2915 case IP_VERSION(2, 6, 0):
2916 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2917 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2918 break;
2919 case IP_VERSION(3, 0, 0):
2920 case IP_VERSION(3, 0, 16):
2921 case IP_VERSION(3, 1, 1):
2922 case IP_VERSION(3, 1, 2):
2923 case IP_VERSION(3, 0, 2):
2924 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2925 if (!amdgpu_sriov_vf(adev))
2926 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2927 break;
2928 case IP_VERSION(3, 0, 33):
2929 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2930 break;
2931 case IP_VERSION(4, 0, 0):
2932 case IP_VERSION(4, 0, 2):
2933 case IP_VERSION(4, 0, 4):
2934 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2935 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2936 break;
2937 case IP_VERSION(4, 0, 3):
2938 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2939 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2940 break;
2941 case IP_VERSION(4, 0, 5):
2942 case IP_VERSION(4, 0, 6):
2943 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2944 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2945 break;
2946 case IP_VERSION(5, 0, 0):
2947 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2948 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2949 break;
2950 case IP_VERSION(5, 3, 0):
2951 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2952 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block);
2953 break;
2954 case IP_VERSION(5, 0, 1):
2955 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
2956 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);
2957 break;
2958 case IP_VERSION(5, 0, 2):
2959 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block);
2960 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block);
2961 break;
2962 default:
2963 dev_err(adev->dev,
2964 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2965 vcn_version);
2966 return -EINVAL;
2967 }
2968 }
2969 return 0;
2970 }
2971
amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device * adev)2972 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2973 {
2974 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2975 case IP_VERSION(11, 0, 0):
2976 case IP_VERSION(11, 0, 1):
2977 case IP_VERSION(11, 0, 2):
2978 case IP_VERSION(11, 0, 3):
2979 case IP_VERSION(11, 0, 4):
2980 case IP_VERSION(11, 5, 0):
2981 case IP_VERSION(11, 5, 1):
2982 case IP_VERSION(11, 5, 2):
2983 case IP_VERSION(11, 5, 3):
2984 case IP_VERSION(11, 5, 4):
2985 case IP_VERSION(11, 5, 6):
2986 case IP_VERSION(11, 7, 0):
2987 case IP_VERSION(11, 7, 1):
2988 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2989 adev->enable_mes = true;
2990 adev->enable_mes_kiq = true;
2991 break;
2992 case IP_VERSION(12, 0, 0):
2993 case IP_VERSION(12, 0, 1):
2994 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2995 adev->enable_mes = true;
2996 adev->enable_mes_kiq = true;
2997 if (amdgpu_uni_mes)
2998 adev->enable_uni_mes = true;
2999 break;
3000 case IP_VERSION(12, 1, 0):
3001 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block);
3002 adev->enable_mes = true;
3003 adev->enable_mes_kiq = true;
3004 if (amdgpu_uni_mes)
3005 adev->enable_uni_mes = true;
3006 break;
3007 default:
3008 break;
3009 }
3010 return 0;
3011 }
3012
amdgpu_discovery_init_soc_config(struct amdgpu_device * adev)3013 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
3014 {
3015 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3016 case IP_VERSION(9, 4, 3):
3017 case IP_VERSION(9, 4, 4):
3018 case IP_VERSION(9, 5, 0):
3019 aqua_vanjaram_init_soc_config(adev);
3020 break;
3021 case IP_VERSION(12, 1, 0):
3022 soc_v1_0_init_soc_config(adev);
3023 break;
3024 default:
3025 break;
3026 }
3027 }
3028
amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device * adev)3029 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
3030 {
3031 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
3032 case IP_VERSION(6, 1, 0):
3033 case IP_VERSION(6, 1, 1):
3034 case IP_VERSION(6, 1, 3):
3035 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
3036 break;
3037 case IP_VERSION(2, 0, 0):
3038 case IP_VERSION(2, 2, 0):
3039 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block);
3040 break;
3041 default:
3042 break;
3043 }
3044
3045 return 0;
3046 }
3047
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device * adev)3048 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
3049 {
3050 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
3051 case IP_VERSION(4, 0, 5):
3052 case IP_VERSION(4, 0, 6):
3053 if (amdgpu_umsch_mm & 0x1) {
3054 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
3055 adev->enable_umsch_mm = true;
3056 }
3057 break;
3058 default:
3059 break;
3060 }
3061
3062 return 0;
3063 }
3064
amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device * adev)3065 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
3066 {
3067 #if defined(CONFIG_DRM_AMD_ISP)
3068 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
3069 case IP_VERSION(4, 1, 0):
3070 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
3071 break;
3072 case IP_VERSION(4, 1, 1):
3073 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
3074 break;
3075 default:
3076 break;
3077 }
3078 #endif
3079
3080 return 0;
3081 }
3082
amdgpu_discovery_set_ip_blocks(struct amdgpu_device * adev)3083 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
3084 {
3085 int r;
3086
3087 switch (adev->asic_type) {
3088 case CHIP_VEGA10:
3089 /* This is not fatal. We only need the discovery
3090 * binary for sysfs. We don't need it for a
3091 * functional system.
3092 */
3093 amdgpu_discovery_init(adev);
3094 vega10_reg_base_init(adev);
3095 adev->sdma.num_instances = 2;
3096 adev->sdma.sdma_mask = 3;
3097 adev->gmc.num_umc = 4;
3098 adev->gfx.xcc_mask = 1;
3099 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3100 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
3101 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
3102 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
3103 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
3104 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
3105 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3106 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
3107 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
3108 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3109 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3110 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3111 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
3112 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
3113 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3114 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3115 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
3116 break;
3117 case CHIP_VEGA12:
3118 /* This is not fatal. We only need the discovery
3119 * binary for sysfs. We don't need it for a
3120 * functional system.
3121 */
3122 amdgpu_discovery_init(adev);
3123 vega10_reg_base_init(adev);
3124 adev->sdma.num_instances = 2;
3125 adev->sdma.sdma_mask = 3;
3126 adev->gmc.num_umc = 4;
3127 adev->gfx.xcc_mask = 1;
3128 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3129 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
3130 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
3131 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
3132 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
3133 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
3134 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
3135 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
3136 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
3137 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
3138 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
3139 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
3140 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
3141 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
3142 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
3143 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
3144 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
3145 break;
3146 case CHIP_RAVEN:
3147 /* This is not fatal. We only need the discovery
3148 * binary for sysfs. We don't need it for a
3149 * functional system.
3150 */
3151 amdgpu_discovery_init(adev);
3152 vega10_reg_base_init(adev);
3153 adev->sdma.num_instances = 1;
3154 adev->sdma.sdma_mask = 1;
3155 adev->vcn.num_vcn_inst = 1;
3156 adev->gmc.num_umc = 2;
3157 adev->gfx.xcc_mask = 1;
3158 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
3159 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3160 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
3161 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
3162 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
3163 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
3164 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
3165 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
3166 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
3167 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
3168 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
3169 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
3170 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
3171 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
3172 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
3173 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
3174 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3175 } else {
3176 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3177 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
3178 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
3179 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
3180 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
3181 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
3182 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
3183 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
3184 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
3185 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
3186 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
3187 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
3188 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
3189 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
3190 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
3191 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
3192 }
3193 break;
3194 case CHIP_VEGA20:
3195 /* This is not fatal. We only need the discovery
3196 * binary for sysfs. We don't need it for a
3197 * functional system.
3198 */
3199 amdgpu_discovery_init(adev);
3200 vega20_reg_base_init(adev);
3201 adev->sdma.num_instances = 2;
3202 adev->sdma.sdma_mask = 3;
3203 adev->gmc.num_umc = 8;
3204 adev->gfx.xcc_mask = 1;
3205 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3206 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
3207 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
3208 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
3209 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
3210 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
3211 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
3212 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
3213 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
3214 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
3215 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3216 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
3217 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
3218 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
3219 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
3220 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
3221 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
3222 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
3223 break;
3224 case CHIP_ARCTURUS:
3225 /* This is not fatal. We only need the discovery
3226 * binary for sysfs. We don't need it for a
3227 * functional system.
3228 */
3229 amdgpu_discovery_init(adev);
3230 arct_reg_base_init(adev);
3231 adev->sdma.num_instances = 8;
3232 adev->sdma.sdma_mask = 0xff;
3233 adev->vcn.num_vcn_inst = 2;
3234 adev->gmc.num_umc = 8;
3235 adev->gfx.xcc_mask = 1;
3236 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3237 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
3238 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
3239 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
3240 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
3241 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
3242 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
3243 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
3244 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
3245 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
3246 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
3247 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
3248 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
3249 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
3250 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
3251 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
3252 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
3253 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
3254 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
3255 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
3256 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
3257 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
3258 break;
3259 case CHIP_ALDEBARAN:
3260 /* This is not fatal. We only need the discovery
3261 * binary for sysfs. We don't need it for a
3262 * functional system.
3263 */
3264 amdgpu_discovery_init(adev);
3265 aldebaran_reg_base_init(adev);
3266 adev->sdma.num_instances = 5;
3267 adev->sdma.sdma_mask = 0x1f;
3268 adev->vcn.num_vcn_inst = 2;
3269 adev->gmc.num_umc = 4;
3270 adev->gfx.xcc_mask = 1;
3271 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3272 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
3273 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
3274 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
3275 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
3276 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
3277 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
3278 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
3279 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
3280 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
3281 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
3282 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
3283 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
3284 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
3285 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
3286 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
3287 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
3288 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
3289 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
3290 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
3291 break;
3292 case CHIP_CYAN_SKILLFISH:
3293 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
3294 r = amdgpu_discovery_reg_base_init(adev);
3295 if (r)
3296 return -EINVAL;
3297
3298 amdgpu_discovery_harvest_ip(adev);
3299 amdgpu_discovery_get_gfx_info(adev);
3300 amdgpu_discovery_get_mall_info(adev);
3301 amdgpu_discovery_get_vcn_info(adev);
3302 } else {
3303 cyan_skillfish_reg_base_init(adev);
3304 adev->sdma.num_instances = 2;
3305 adev->sdma.sdma_mask = 3;
3306 adev->gfx.xcc_mask = 1;
3307 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3308 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3);
3309 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);
3310 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1);
3311 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1);
3312 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1);
3313 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0);
3314 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);
3315 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);
3316 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8);
3317 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8);
3318 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1);
3319 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8);
3320 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3);
3321 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);
3322 }
3323 break;
3324 default:
3325 r = amdgpu_discovery_reg_base_init(adev);
3326 if (r) {
3327 drm_err(&adev->ddev, "discovery failed: %d\n", r);
3328 return r;
3329 }
3330
3331 amdgpu_discovery_harvest_ip(adev);
3332 amdgpu_discovery_get_gfx_info(adev);
3333 amdgpu_discovery_get_mall_info(adev);
3334 amdgpu_discovery_get_vcn_info(adev);
3335 break;
3336 }
3337
3338 amdgpu_discovery_init_soc_config(adev);
3339 amdgpu_discovery_sysfs_init(adev);
3340
3341 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3342 case IP_VERSION(9, 0, 1):
3343 case IP_VERSION(9, 2, 1):
3344 case IP_VERSION(9, 4, 0):
3345 case IP_VERSION(9, 4, 1):
3346 case IP_VERSION(9, 4, 2):
3347 case IP_VERSION(9, 4, 3):
3348 case IP_VERSION(9, 4, 4):
3349 case IP_VERSION(9, 5, 0):
3350 adev->family = AMDGPU_FAMILY_AI;
3351 break;
3352 case IP_VERSION(9, 1, 0):
3353 case IP_VERSION(9, 2, 2):
3354 case IP_VERSION(9, 3, 0):
3355 adev->family = AMDGPU_FAMILY_RV;
3356 break;
3357 case IP_VERSION(10, 1, 10):
3358 case IP_VERSION(10, 1, 1):
3359 case IP_VERSION(10, 1, 2):
3360 case IP_VERSION(10, 1, 3):
3361 case IP_VERSION(10, 1, 4):
3362 case IP_VERSION(10, 3, 0):
3363 case IP_VERSION(10, 3, 2):
3364 case IP_VERSION(10, 3, 4):
3365 case IP_VERSION(10, 3, 5):
3366 adev->family = AMDGPU_FAMILY_NV;
3367 break;
3368 case IP_VERSION(10, 3, 1):
3369 adev->family = AMDGPU_FAMILY_VGH;
3370 adev->apu_flags |= AMD_APU_IS_VANGOGH;
3371 break;
3372 case IP_VERSION(10, 3, 3):
3373 adev->family = AMDGPU_FAMILY_YC;
3374 break;
3375 case IP_VERSION(10, 3, 6):
3376 adev->family = AMDGPU_FAMILY_GC_10_3_6;
3377 break;
3378 case IP_VERSION(10, 3, 7):
3379 adev->family = AMDGPU_FAMILY_GC_10_3_7;
3380 break;
3381 case IP_VERSION(11, 0, 0):
3382 case IP_VERSION(11, 0, 2):
3383 case IP_VERSION(11, 0, 3):
3384 adev->family = AMDGPU_FAMILY_GC_11_0_0;
3385 break;
3386 case IP_VERSION(11, 0, 1):
3387 case IP_VERSION(11, 0, 4):
3388 adev->family = AMDGPU_FAMILY_GC_11_0_1;
3389 break;
3390 case IP_VERSION(11, 5, 0):
3391 case IP_VERSION(11, 5, 1):
3392 case IP_VERSION(11, 5, 2):
3393 case IP_VERSION(11, 5, 3):
3394 case IP_VERSION(11, 5, 4):
3395 case IP_VERSION(11, 5, 6):
3396 adev->family = AMDGPU_FAMILY_GC_11_5_0;
3397 break;
3398 case IP_VERSION(11, 7, 0):
3399 case IP_VERSION(11, 7, 1):
3400 adev->family = AMDGPU_FAMILY_GC_11_5_4;
3401 break;
3402 case IP_VERSION(12, 0, 0):
3403 case IP_VERSION(12, 0, 1):
3404 case IP_VERSION(12, 1, 0):
3405 adev->family = AMDGPU_FAMILY_GC_12_0_0;
3406 break;
3407 default:
3408 return -EINVAL;
3409 }
3410
3411 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3412 case IP_VERSION(9, 1, 0):
3413 case IP_VERSION(9, 2, 2):
3414 case IP_VERSION(9, 3, 0):
3415 case IP_VERSION(10, 1, 3):
3416 case IP_VERSION(10, 1, 4):
3417 case IP_VERSION(10, 3, 1):
3418 case IP_VERSION(10, 3, 3):
3419 case IP_VERSION(10, 3, 6):
3420 case IP_VERSION(10, 3, 7):
3421 case IP_VERSION(11, 0, 1):
3422 case IP_VERSION(11, 0, 4):
3423 case IP_VERSION(11, 5, 0):
3424 case IP_VERSION(11, 5, 1):
3425 case IP_VERSION(11, 5, 2):
3426 case IP_VERSION(11, 5, 3):
3427 case IP_VERSION(11, 5, 4):
3428 case IP_VERSION(11, 5, 6):
3429 case IP_VERSION(11, 7, 0):
3430 case IP_VERSION(11, 7, 1):
3431 adev->flags |= AMD_IS_APU;
3432 break;
3433 default:
3434 break;
3435 }
3436
3437 /* set NBIO version */
3438 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
3439 case IP_VERSION(6, 1, 0):
3440 case IP_VERSION(6, 2, 0):
3441 adev->nbio.funcs = &nbio_v6_1_funcs;
3442 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
3443 break;
3444 case IP_VERSION(7, 0, 0):
3445 case IP_VERSION(7, 0, 1):
3446 case IP_VERSION(2, 5, 0):
3447 adev->nbio.funcs = &nbio_v7_0_funcs;
3448 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
3449 break;
3450 case IP_VERSION(7, 4, 0):
3451 case IP_VERSION(7, 4, 1):
3452 case IP_VERSION(7, 4, 4):
3453 adev->nbio.funcs = &nbio_v7_4_funcs;
3454 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
3455 break;
3456 case IP_VERSION(7, 9, 0):
3457 case IP_VERSION(7, 9, 1):
3458 adev->nbio.funcs = &nbio_v7_9_funcs;
3459 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
3460 break;
3461 case IP_VERSION(7, 11, 0):
3462 case IP_VERSION(7, 11, 1):
3463 case IP_VERSION(7, 11, 2):
3464 case IP_VERSION(7, 11, 3):
3465 adev->nbio.funcs = &nbio_v7_11_funcs;
3466 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
3467 break;
3468 case IP_VERSION(7, 2, 0):
3469 case IP_VERSION(7, 2, 1):
3470 case IP_VERSION(7, 3, 0):
3471 case IP_VERSION(7, 5, 0):
3472 case IP_VERSION(7, 5, 1):
3473 adev->nbio.funcs = &nbio_v7_2_funcs;
3474 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
3475 break;
3476 case IP_VERSION(2, 1, 1):
3477 case IP_VERSION(2, 3, 0):
3478 case IP_VERSION(2, 3, 1):
3479 case IP_VERSION(2, 3, 2):
3480 case IP_VERSION(3, 3, 0):
3481 case IP_VERSION(3, 3, 1):
3482 case IP_VERSION(3, 3, 2):
3483 case IP_VERSION(3, 3, 3):
3484 adev->nbio.funcs = &nbio_v2_3_funcs;
3485 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
3486 break;
3487 case IP_VERSION(4, 3, 0):
3488 case IP_VERSION(4, 3, 1):
3489 if (amdgpu_sriov_vf(adev))
3490 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
3491 else
3492 adev->nbio.funcs = &nbio_v4_3_funcs;
3493 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
3494 break;
3495 case IP_VERSION(7, 7, 0):
3496 case IP_VERSION(7, 7, 1):
3497 adev->nbio.funcs = &nbio_v7_7_funcs;
3498 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
3499 break;
3500 case IP_VERSION(6, 3, 1):
3501 case IP_VERSION(7, 11, 4):
3502 case IP_VERSION(7, 11, 5):
3503 adev->nbio.funcs = &nbif_v6_3_1_funcs;
3504 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
3505 break;
3506 case IP_VERSION(6, 3, 2):
3507 adev->nbio.funcs = &nbio_v6_3_2_funcs;
3508 break;
3509 default:
3510 break;
3511 }
3512
3513 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
3514 case IP_VERSION(4, 0, 0):
3515 case IP_VERSION(4, 0, 1):
3516 case IP_VERSION(4, 1, 0):
3517 case IP_VERSION(4, 1, 1):
3518 case IP_VERSION(4, 1, 2):
3519 case IP_VERSION(4, 2, 0):
3520 case IP_VERSION(4, 2, 1):
3521 case IP_VERSION(4, 4, 0):
3522 case IP_VERSION(4, 4, 2):
3523 case IP_VERSION(4, 4, 5):
3524 adev->hdp.funcs = &hdp_v4_0_funcs;
3525 break;
3526 case IP_VERSION(5, 0, 0):
3527 case IP_VERSION(5, 0, 1):
3528 case IP_VERSION(5, 0, 2):
3529 case IP_VERSION(5, 0, 3):
3530 case IP_VERSION(5, 0, 4):
3531 case IP_VERSION(5, 2, 0):
3532 adev->hdp.funcs = &hdp_v5_0_funcs;
3533 break;
3534 case IP_VERSION(5, 2, 1):
3535 adev->hdp.funcs = &hdp_v5_2_funcs;
3536 break;
3537 case IP_VERSION(6, 0, 0):
3538 case IP_VERSION(6, 0, 1):
3539 case IP_VERSION(6, 1, 0):
3540 case IP_VERSION(6, 1, 1):
3541 case IP_VERSION(6, 4, 0):
3542 adev->hdp.funcs = &hdp_v6_0_funcs;
3543 break;
3544 case IP_VERSION(7, 0, 0):
3545 adev->hdp.funcs = &hdp_v7_0_funcs;
3546 break;
3547 default:
3548 break;
3549 }
3550
3551 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
3552 case IP_VERSION(3, 6, 0):
3553 case IP_VERSION(3, 6, 1):
3554 case IP_VERSION(3, 6, 2):
3555 adev->df.funcs = &df_v3_6_funcs;
3556 break;
3557 case IP_VERSION(2, 1, 0):
3558 case IP_VERSION(2, 1, 1):
3559 case IP_VERSION(2, 5, 0):
3560 case IP_VERSION(3, 5, 1):
3561 case IP_VERSION(3, 5, 2):
3562 adev->df.funcs = &df_v1_7_funcs;
3563 break;
3564 case IP_VERSION(4, 3, 0):
3565 adev->df.funcs = &df_v4_3_funcs;
3566 break;
3567 case IP_VERSION(4, 6, 2):
3568 adev->df.funcs = &df_v4_6_2_funcs;
3569 break;
3570 case IP_VERSION(4, 15, 0):
3571 case IP_VERSION(4, 15, 1):
3572 adev->df.funcs = &df_v4_15_funcs;
3573 break;
3574 default:
3575 break;
3576 }
3577
3578 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
3579 case IP_VERSION(9, 0, 0):
3580 case IP_VERSION(9, 0, 1):
3581 case IP_VERSION(10, 0, 0):
3582 case IP_VERSION(10, 0, 1):
3583 case IP_VERSION(10, 0, 2):
3584 adev->smuio.funcs = &smuio_v9_0_funcs;
3585 break;
3586 case IP_VERSION(11, 0, 0):
3587 case IP_VERSION(11, 0, 2):
3588 case IP_VERSION(11, 0, 3):
3589 case IP_VERSION(11, 0, 4):
3590 case IP_VERSION(11, 0, 7):
3591 case IP_VERSION(11, 0, 8):
3592 adev->smuio.funcs = &smuio_v11_0_funcs;
3593 break;
3594 case IP_VERSION(11, 0, 6):
3595 case IP_VERSION(11, 0, 10):
3596 case IP_VERSION(11, 0, 11):
3597 case IP_VERSION(11, 5, 0):
3598 case IP_VERSION(11, 5, 2):
3599 case IP_VERSION(13, 0, 1):
3600 case IP_VERSION(13, 0, 9):
3601 case IP_VERSION(13, 0, 10):
3602 adev->smuio.funcs = &smuio_v11_0_6_funcs;
3603 break;
3604 case IP_VERSION(13, 0, 2):
3605 adev->smuio.funcs = &smuio_v13_0_funcs;
3606 break;
3607 case IP_VERSION(13, 0, 3):
3608 case IP_VERSION(13, 0, 11):
3609 adev->smuio.funcs = &smuio_v13_0_3_funcs;
3610 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
3611 adev->flags |= AMD_IS_APU;
3612 }
3613 break;
3614 case IP_VERSION(13, 0, 6):
3615 case IP_VERSION(13, 0, 8):
3616 case IP_VERSION(14, 0, 0):
3617 case IP_VERSION(14, 0, 1):
3618 adev->smuio.funcs = &smuio_v13_0_6_funcs;
3619 break;
3620 case IP_VERSION(14, 0, 2):
3621 adev->smuio.funcs = &smuio_v14_0_2_funcs;
3622 break;
3623 case IP_VERSION(15, 0, 0):
3624 case IP_VERSION(15, 0, 5):
3625 adev->smuio.funcs = &smuio_v15_0_0_funcs;
3626 break;
3627 case IP_VERSION(15, 0, 8):
3628 adev->smuio.funcs = &smuio_v15_0_8_funcs;
3629 break;
3630 default:
3631 break;
3632 }
3633
3634 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
3635 case IP_VERSION(6, 0, 0):
3636 case IP_VERSION(6, 0, 1):
3637 case IP_VERSION(6, 0, 2):
3638 case IP_VERSION(6, 0, 3):
3639 adev->lsdma.funcs = &lsdma_v6_0_funcs;
3640 break;
3641 case IP_VERSION(7, 0, 0):
3642 case IP_VERSION(7, 0, 1):
3643 adev->lsdma.funcs = &lsdma_v7_0_funcs;
3644 break;
3645 case IP_VERSION(7, 1, 0):
3646 adev->lsdma.funcs = &lsdma_v7_1_funcs;
3647 break;
3648 default:
3649 break;
3650 }
3651
3652 r = amdgpu_discovery_set_common_ip_blocks(adev);
3653 if (r)
3654 return r;
3655
3656 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
3657 if (r)
3658 return r;
3659
3660 /* For SR-IOV, PSP needs to be initialized before IH */
3661 if (amdgpu_sriov_vf(adev)) {
3662 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3663 if (r)
3664 return r;
3665 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3666 if (r)
3667 return r;
3668 } else {
3669 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3670 if (r)
3671 return r;
3672
3673 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3674 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3675 if (r)
3676 return r;
3677 }
3678 }
3679
3680 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3681 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3682 if (r)
3683 return r;
3684 }
3685
3686 r = amdgpu_discovery_set_display_ip_blocks(adev);
3687 if (r)
3688 return r;
3689
3690 r = amdgpu_discovery_set_gc_ip_blocks(adev);
3691 if (r)
3692 return r;
3693
3694 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
3695 if (r)
3696 return r;
3697
3698 r = amdgpu_discovery_set_ras_ip_blocks(adev);
3699 if (r)
3700 return r;
3701
3702 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
3703 !amdgpu_sriov_vf(adev) &&
3704 amdgpu_dpm == 1) ||
3705 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO &&
3706 amdgpu_dpm == 1)) {
3707 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3708 if (r)
3709 return r;
3710 }
3711
3712 r = amdgpu_discovery_set_mm_ip_blocks(adev);
3713 if (r)
3714 return r;
3715
3716 r = amdgpu_discovery_set_mes_ip_blocks(adev);
3717 if (r)
3718 return r;
3719
3720 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
3721 if (r)
3722 return r;
3723
3724 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
3725 if (r)
3726 return r;
3727
3728 r = amdgpu_discovery_set_isp_ip_blocks(adev);
3729 if (r)
3730 return r;
3731 return 0;
3732 }
3733
amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device * adev,uint16_t * major,uint16_t * minor)3734 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
3735 uint16_t *major, uint16_t *minor)
3736 {
3737 uint8_t *discovery_bin = adev->discovery.bin;
3738 struct table_info *info;
3739 union gc_info *gc_info;
3740 u16 offset;
3741
3742 if (!discovery_bin)
3743 return -EINVAL;
3744 if (amdgpu_discovery_get_table_info(adev, &info, GC))
3745 return -EINVAL;
3746
3747 offset = le16_to_cpu(info->offset);
3748 if (!offset)
3749 return -EINVAL;
3750
3751 gc_info = (union gc_info *)(discovery_bin + offset);
3752
3753 if (major)
3754 *major = le16_to_cpu(gc_info->v1.header.version_major);
3755 if (minor)
3756 *minor = le16_to_cpu(gc_info->v1.header.version_minor);
3757 return 0;
3758 }
3759