1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/perf_event.h>
3 #include <linux/jump_label.h>
4 #include <linux/export.h>
5 #include <linux/kvm_types.h>
6 #include <linux/types.h>
7 #include <linux/init.h>
8 #include <linux/slab.h>
9 #include <linux/delay.h>
10 #include <linux/jiffies.h>
11
12 #include <asm/apicdef.h>
13 #include <asm/apic.h>
14 #include <asm/cpuid/api.h>
15 #include <asm/msr.h>
16 #include <asm/nmi.h>
17
18 #include "../perf_event.h"
19
20 static DEFINE_PER_CPU(unsigned long, perf_nmi_tstamp);
21 static unsigned long perf_nmi_window;
22
23 /* AMD Event 0xFFF: Merge. Used with Large Increment per Cycle events */
24 #define AMD_MERGE_EVENT ((0xFULL << 32) | 0xFFULL)
25 #define AMD_MERGE_EVENT_ENABLE (AMD_MERGE_EVENT | ARCH_PERFMON_EVENTSEL_ENABLE)
26
27 /* PMC Enable and Overflow bits for PerfCntrGlobal* registers */
28 static u64 amd_pmu_global_cntr_mask __read_mostly;
29
30 static __initconst const u64 amd_hw_cache_event_ids
31 [PERF_COUNT_HW_CACHE_MAX]
32 [PERF_COUNT_HW_CACHE_OP_MAX]
33 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
34 {
35 [ C(L1D) ] = {
36 [ C(OP_READ) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
38 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
39 },
40 [ C(OP_WRITE) ] = {
41 [ C(RESULT_ACCESS) ] = 0,
42 [ C(RESULT_MISS) ] = 0,
43 },
44 [ C(OP_PREFETCH) ] = {
45 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
46 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
47 },
48 },
49 [ C(L1I ) ] = {
50 [ C(OP_READ) ] = {
51 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
52 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
53 },
54 [ C(OP_WRITE) ] = {
55 [ C(RESULT_ACCESS) ] = -1,
56 [ C(RESULT_MISS) ] = -1,
57 },
58 [ C(OP_PREFETCH) ] = {
59 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
60 [ C(RESULT_MISS) ] = 0,
61 },
62 },
63 [ C(LL ) ] = {
64 [ C(OP_READ) ] = {
65 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
66 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
67 },
68 [ C(OP_WRITE) ] = {
69 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
70 [ C(RESULT_MISS) ] = 0,
71 },
72 [ C(OP_PREFETCH) ] = {
73 [ C(RESULT_ACCESS) ] = 0,
74 [ C(RESULT_MISS) ] = 0,
75 },
76 },
77 [ C(DTLB) ] = {
78 [ C(OP_READ) ] = {
79 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
80 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
81 },
82 [ C(OP_WRITE) ] = {
83 [ C(RESULT_ACCESS) ] = 0,
84 [ C(RESULT_MISS) ] = 0,
85 },
86 [ C(OP_PREFETCH) ] = {
87 [ C(RESULT_ACCESS) ] = 0,
88 [ C(RESULT_MISS) ] = 0,
89 },
90 },
91 [ C(ITLB) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
94 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
95 },
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = -1,
98 [ C(RESULT_MISS) ] = -1,
99 },
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = -1,
102 [ C(RESULT_MISS) ] = -1,
103 },
104 },
105 [ C(BPU ) ] = {
106 [ C(OP_READ) ] = {
107 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
108 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
109 },
110 [ C(OP_WRITE) ] = {
111 [ C(RESULT_ACCESS) ] = -1,
112 [ C(RESULT_MISS) ] = -1,
113 },
114 [ C(OP_PREFETCH) ] = {
115 [ C(RESULT_ACCESS) ] = -1,
116 [ C(RESULT_MISS) ] = -1,
117 },
118 },
119 [ C(NODE) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
122 [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
123 },
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = -1,
126 [ C(RESULT_MISS) ] = -1,
127 },
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = -1,
130 [ C(RESULT_MISS) ] = -1,
131 },
132 },
133 };
134
135 static __initconst const u64 amd_hw_cache_event_ids_f17h
136 [PERF_COUNT_HW_CACHE_MAX]
137 [PERF_COUNT_HW_CACHE_OP_MAX]
138 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
139 [C(L1D)] = {
140 [C(OP_READ)] = {
141 [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */
142 [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */
143 },
144 [C(OP_WRITE)] = {
145 [C(RESULT_ACCESS)] = 0,
146 [C(RESULT_MISS)] = 0,
147 },
148 [C(OP_PREFETCH)] = {
149 [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */
150 [C(RESULT_MISS)] = 0,
151 },
152 },
153 [C(L1I)] = {
154 [C(OP_READ)] = {
155 [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */
156 [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */
157 },
158 [C(OP_WRITE)] = {
159 [C(RESULT_ACCESS)] = -1,
160 [C(RESULT_MISS)] = -1,
161 },
162 [C(OP_PREFETCH)] = {
163 [C(RESULT_ACCESS)] = 0,
164 [C(RESULT_MISS)] = 0,
165 },
166 },
167 [C(LL)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = 0,
170 [C(RESULT_MISS)] = 0,
171 },
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = 0,
174 [C(RESULT_MISS)] = 0,
175 },
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = 0,
178 [C(RESULT_MISS)] = 0,
179 },
180 },
181 [C(DTLB)] = {
182 [C(OP_READ)] = {
183 [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */
184 [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */
185 },
186 [C(OP_WRITE)] = {
187 [C(RESULT_ACCESS)] = 0,
188 [C(RESULT_MISS)] = 0,
189 },
190 [C(OP_PREFETCH)] = {
191 [C(RESULT_ACCESS)] = 0,
192 [C(RESULT_MISS)] = 0,
193 },
194 },
195 [C(ITLB)] = {
196 [C(OP_READ)] = {
197 [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */
198 [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */
199 },
200 [C(OP_WRITE)] = {
201 [C(RESULT_ACCESS)] = -1,
202 [C(RESULT_MISS)] = -1,
203 },
204 [C(OP_PREFETCH)] = {
205 [C(RESULT_ACCESS)] = -1,
206 [C(RESULT_MISS)] = -1,
207 },
208 },
209 [C(BPU)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */
212 [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */
213 },
214 [C(OP_WRITE)] = {
215 [C(RESULT_ACCESS)] = -1,
216 [C(RESULT_MISS)] = -1,
217 },
218 [C(OP_PREFETCH)] = {
219 [C(RESULT_ACCESS)] = -1,
220 [C(RESULT_MISS)] = -1,
221 },
222 },
223 [C(NODE)] = {
224 [C(OP_READ)] = {
225 [C(RESULT_ACCESS)] = 0,
226 [C(RESULT_MISS)] = 0,
227 },
228 [C(OP_WRITE)] = {
229 [C(RESULT_ACCESS)] = -1,
230 [C(RESULT_MISS)] = -1,
231 },
232 [C(OP_PREFETCH)] = {
233 [C(RESULT_ACCESS)] = -1,
234 [C(RESULT_MISS)] = -1,
235 },
236 },
237 };
238
239 /*
240 * AMD Performance Monitor K7 and later, up to and including Family 16h:
241 */
242 static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
243 {
244 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
245 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
246 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d,
247 [PERF_COUNT_HW_CACHE_MISSES] = 0x077e,
248 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
249 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
250 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */
251 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */
252 };
253
254 /*
255 * AMD Performance Monitor Family 17h and later:
256 */
257 static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
258 {
259 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
260 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
261 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
262 [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
263 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
264 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
265 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287,
266 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187,
267 };
268
269 static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
270 {
271 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
272 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
273 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
274 [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
275 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
276 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
277 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
278 };
279
280 static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
281 {
282 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
283 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
284 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60,
285 [PERF_COUNT_HW_CACHE_MISSES] = 0x0964,
286 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2,
287 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3,
288 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
289 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x100000120,
290 };
291
amd_pmu_event_map(int hw_event)292 static u64 amd_pmu_event_map(int hw_event)
293 {
294 if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
295 return amd_zen4_perfmon_event_map[hw_event];
296
297 if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
298 return amd_zen2_perfmon_event_map[hw_event];
299
300 if (cpu_feature_enabled(X86_FEATURE_ZEN1))
301 return amd_zen1_perfmon_event_map[hw_event];
302
303 return amd_perfmon_event_map[hw_event];
304 }
305
306 /*
307 * Previously calculated offsets
308 */
309 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
310 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
311
312 /*
313 * Legacy CPUs:
314 * 4 counters starting at 0xc0010000 each offset by 1
315 *
316 * CPUs with core performance counter extensions:
317 * 6 counters starting at 0xc0010200 each offset by 2
318 */
amd_pmu_addr_offset(int index,bool eventsel)319 static inline int amd_pmu_addr_offset(int index, bool eventsel)
320 {
321 int offset;
322
323 if (!index)
324 return index;
325
326 if (eventsel)
327 offset = event_offsets[index];
328 else
329 offset = count_offsets[index];
330
331 if (offset)
332 return offset;
333
334 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
335 offset = index;
336 else
337 offset = index << 1;
338
339 if (eventsel)
340 event_offsets[index] = offset;
341 else
342 count_offsets[index] = offset;
343
344 return offset;
345 }
346
347 /*
348 * AMD64 events are detected based on their event codes.
349 */
amd_get_event_code(struct hw_perf_event * hwc)350 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
351 {
352 return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
353 }
354
amd_is_pair_event_code(struct hw_perf_event * hwc)355 static inline bool amd_is_pair_event_code(struct hw_perf_event *hwc)
356 {
357 if (!(x86_pmu.flags & PMU_FL_PAIR))
358 return false;
359
360 switch (amd_get_event_code(hwc)) {
361 case 0x003: return true; /* Retired SSE/AVX FLOPs */
362 default: return false;
363 }
364 }
365
366 DEFINE_STATIC_CALL_RET0(amd_pmu_branch_hw_config, *x86_pmu.hw_config);
367
amd_core_hw_config(struct perf_event * event)368 static int amd_core_hw_config(struct perf_event *event)
369 {
370 if (event->attr.exclude_host && event->attr.exclude_guest)
371 /*
372 * When HO == GO == 1 the hardware treats that as GO == HO == 0
373 * and will count in both modes. We don't want to count in that
374 * case so we emulate no-counting by setting US = OS = 0.
375 */
376 event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
377 ARCH_PERFMON_EVENTSEL_OS);
378 else if (event->attr.exclude_host)
379 event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
380 else if (event->attr.exclude_guest)
381 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
382
383 if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw))
384 event->hw.flags |= PERF_X86_EVENT_PAIR;
385
386 if (has_branch_stack(event))
387 return static_call(amd_pmu_branch_hw_config)(event);
388
389 return 0;
390 }
391
amd_is_nb_event(struct hw_perf_event * hwc)392 static inline int amd_is_nb_event(struct hw_perf_event *hwc)
393 {
394 return (hwc->config & 0xe0) == 0xe0;
395 }
396
amd_has_nb(struct cpu_hw_events * cpuc)397 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
398 {
399 struct amd_nb *nb = cpuc->amd_nb;
400
401 return nb && nb->nb_id != -1;
402 }
403
amd_pmu_hw_config(struct perf_event * event)404 static int amd_pmu_hw_config(struct perf_event *event)
405 {
406 int ret;
407
408 /* pass precise event sampling to ibs: */
409 if (event->attr.precise_ip && get_ibs_caps())
410 return forward_event_to_ibs(event);
411
412 if (has_branch_stack(event) && !x86_pmu.lbr_nr)
413 return -EOPNOTSUPP;
414
415 ret = x86_pmu_hw_config(event);
416 if (ret)
417 return ret;
418
419 if (event->attr.type == PERF_TYPE_RAW)
420 event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
421
422 return amd_core_hw_config(event);
423 }
424
__amd_put_nb_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)425 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
426 struct perf_event *event)
427 {
428 struct amd_nb *nb = cpuc->amd_nb;
429 int i;
430
431 /*
432 * need to scan whole list because event may not have
433 * been assigned during scheduling
434 *
435 * no race condition possible because event can only
436 * be removed on one CPU at a time AND PMU is disabled
437 * when we come here
438 */
439 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
440 struct perf_event *tmp = event;
441
442 if (try_cmpxchg(nb->owners + i, &tmp, NULL))
443 break;
444 }
445 }
446
447 /*
448 * AMD64 NorthBridge events need special treatment because
449 * counter access needs to be synchronized across all cores
450 * of a package. Refer to BKDG section 3.12
451 *
452 * NB events are events measuring L3 cache, Hypertransport
453 * traffic. They are identified by an event code >= 0xe00.
454 * They measure events on the NorthBride which is shared
455 * by all cores on a package. NB events are counted on a
456 * shared set of counters. When a NB event is programmed
457 * in a counter, the data actually comes from a shared
458 * counter. Thus, access to those counters needs to be
459 * synchronized.
460 *
461 * We implement the synchronization such that no two cores
462 * can be measuring NB events using the same counters. Thus,
463 * we maintain a per-NB allocation table. The available slot
464 * is propagated using the event_constraint structure.
465 *
466 * We provide only one choice for each NB event based on
467 * the fact that only NB events have restrictions. Consequently,
468 * if a counter is available, there is a guarantee the NB event
469 * will be assigned to it. If no slot is available, an empty
470 * constraint is returned and scheduling will eventually fail
471 * for this event.
472 *
473 * Note that all cores attached the same NB compete for the same
474 * counters to host NB events, this is why we use atomic ops. Some
475 * multi-chip CPUs may have more than one NB.
476 *
477 * Given that resources are allocated (cmpxchg), they must be
478 * eventually freed for others to use. This is accomplished by
479 * calling __amd_put_nb_event_constraints()
480 *
481 * Non NB events are not impacted by this restriction.
482 */
483 static struct event_constraint *
__amd_get_nb_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct event_constraint * c)484 __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
485 struct event_constraint *c)
486 {
487 struct hw_perf_event *hwc = &event->hw;
488 struct amd_nb *nb = cpuc->amd_nb;
489 struct perf_event *old;
490 int idx, new = -1;
491
492 if (!c)
493 c = &unconstrained;
494
495 if (cpuc->is_fake)
496 return c;
497
498 /*
499 * detect if already present, if so reuse
500 *
501 * cannot merge with actual allocation
502 * because of possible holes
503 *
504 * event can already be present yet not assigned (in hwc->idx)
505 * because of successive calls to x86_schedule_events() from
506 * hw_perf_group_sched_in() without hw_perf_enable()
507 */
508 for_each_set_bit(idx, c->idxmsk, x86_pmu_max_num_counters(NULL)) {
509 if (new == -1 || hwc->idx == idx)
510 /* assign free slot, prefer hwc->idx */
511 old = cmpxchg(nb->owners + idx, NULL, event);
512 else if (nb->owners[idx] == event)
513 /* event already present */
514 old = event;
515 else
516 continue;
517
518 if (old && old != event)
519 continue;
520
521 /* reassign to this slot */
522 if (new != -1)
523 cmpxchg(nb->owners + new, event, NULL);
524 new = idx;
525
526 /* already present, reuse */
527 if (old == event)
528 break;
529 }
530
531 if (new == -1)
532 return &emptyconstraint;
533
534 return &nb->event_constraints[new];
535 }
536
amd_alloc_nb(int cpu)537 static struct amd_nb *amd_alloc_nb(int cpu)
538 {
539 struct amd_nb *nb;
540 int i;
541
542 nb = kzalloc_node(sizeof(struct amd_nb), GFP_KERNEL, cpu_to_node(cpu));
543 if (!nb)
544 return NULL;
545
546 nb->nb_id = -1;
547
548 /*
549 * initialize all possible NB constraints
550 */
551 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
552 __set_bit(i, nb->event_constraints[i].idxmsk);
553 nb->event_constraints[i].weight = 1;
554 }
555 return nb;
556 }
557
558 typedef void (amd_pmu_branch_reset_t)(void);
559 DEFINE_STATIC_CALL_NULL(amd_pmu_branch_reset, amd_pmu_branch_reset_t);
560
amd_pmu_cpu_reset(int cpu)561 static void amd_pmu_cpu_reset(int cpu)
562 {
563 if (x86_pmu.lbr_nr)
564 static_call(amd_pmu_branch_reset)();
565
566 if (x86_pmu.version < 2)
567 return;
568
569 /* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */
570 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
571
572 /*
573 * Clear freeze and overflow bits i.e. PerfCntrGLobalStatus.LbrFreeze
574 * and PerfCntrGLobalStatus.PerfCntrOvfl
575 */
576 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
577 GLOBAL_STATUS_LBRS_FROZEN | amd_pmu_global_cntr_mask);
578 }
579
amd_pmu_cpu_prepare(int cpu)580 static int amd_pmu_cpu_prepare(int cpu)
581 {
582 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
583
584 cpuc->lbr_sel = kzalloc_node(sizeof(struct er_account), GFP_KERNEL,
585 cpu_to_node(cpu));
586 if (!cpuc->lbr_sel)
587 return -ENOMEM;
588
589 WARN_ON_ONCE(cpuc->amd_nb);
590
591 if (!x86_pmu.amd_nb_constraints)
592 return 0;
593
594 cpuc->amd_nb = amd_alloc_nb(cpu);
595 if (cpuc->amd_nb)
596 return 0;
597
598 kfree(cpuc->lbr_sel);
599 cpuc->lbr_sel = NULL;
600
601 return -ENOMEM;
602 }
603
amd_pmu_cpu_starting(int cpu)604 static void amd_pmu_cpu_starting(int cpu)
605 {
606 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
607 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
608 struct amd_nb *nb;
609 int i, nb_id;
610
611 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
612 amd_pmu_cpu_reset(cpu);
613
614 if (!x86_pmu.amd_nb_constraints)
615 return;
616
617 nb_id = topology_amd_node_id(cpu);
618 WARN_ON_ONCE(nb_id == BAD_APICID);
619
620 for_each_online_cpu(i) {
621 nb = per_cpu(cpu_hw_events, i).amd_nb;
622 if (WARN_ON_ONCE(!nb))
623 continue;
624
625 if (nb->nb_id == nb_id) {
626 *onln = cpuc->amd_nb;
627 cpuc->amd_nb = nb;
628 break;
629 }
630 }
631
632 cpuc->amd_nb->nb_id = nb_id;
633 cpuc->amd_nb->refcnt++;
634 }
635
amd_pmu_cpu_dead(int cpu)636 static void amd_pmu_cpu_dead(int cpu)
637 {
638 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
639
640 kfree(cpuhw->lbr_sel);
641 cpuhw->lbr_sel = NULL;
642
643 if (!x86_pmu.amd_nb_constraints)
644 return;
645
646 if (cpuhw->amd_nb) {
647 struct amd_nb *nb = cpuhw->amd_nb;
648
649 if (nb->nb_id == -1 || --nb->refcnt == 0)
650 kfree(nb);
651
652 cpuhw->amd_nb = NULL;
653 }
654 }
655
amd_pmu_set_global_ctl(u64 ctl)656 static __always_inline void amd_pmu_set_global_ctl(u64 ctl)
657 {
658 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl);
659 }
660
amd_pmu_get_global_status(void)661 static inline u64 amd_pmu_get_global_status(void)
662 {
663 u64 status;
664
665 /* PerfCntrGlobalStatus is read-only */
666 rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);
667
668 return status;
669 }
670
amd_pmu_ack_global_status(u64 status)671 static inline void amd_pmu_ack_global_status(u64 status)
672 {
673 /*
674 * PerfCntrGlobalStatus is read-only but an overflow acknowledgment
675 * mechanism exists; writing 1 to a bit in PerfCntrGlobalStatusClr
676 * clears the same bit in PerfCntrGlobalStatus
677 */
678
679 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);
680 }
681
amd_pmu_test_overflow_topbit(int idx)682 static bool amd_pmu_test_overflow_topbit(int idx)
683 {
684 u64 counter;
685
686 rdmsrq(x86_pmu_event_addr(idx), counter);
687
688 return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1));
689 }
690
amd_pmu_test_overflow_status(int idx)691 static bool amd_pmu_test_overflow_status(int idx)
692 {
693 return amd_pmu_get_global_status() & BIT_ULL(idx);
694 }
695
696 DEFINE_STATIC_CALL(amd_pmu_test_overflow, amd_pmu_test_overflow_topbit);
697
698 /*
699 * When a PMC counter overflows, an NMI is used to process the event and
700 * reset the counter. NMI latency can result in the counter being updated
701 * before the NMI can run, which can result in what appear to be spurious
702 * NMIs. This function is intended to wait for the NMI to run and reset
703 * the counter to avoid possible unhandled NMI messages.
704 */
705 #define OVERFLOW_WAIT_COUNT 50
706
amd_pmu_wait_on_overflow(int idx)707 static void amd_pmu_wait_on_overflow(int idx)
708 {
709 unsigned int i;
710
711 /*
712 * Wait for the counter to be reset if it has overflowed. This loop
713 * should exit very, very quickly, but just in case, don't wait
714 * forever...
715 */
716 for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) {
717 if (!static_call(amd_pmu_test_overflow)(idx))
718 break;
719
720 /* Might be in IRQ context, so can't sleep */
721 udelay(1);
722 }
723 }
724
amd_pmu_check_overflow(void)725 static void amd_pmu_check_overflow(void)
726 {
727 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
728 int idx;
729
730 /*
731 * This shouldn't be called from NMI context, but add a safeguard here
732 * to return, since if we're in NMI context we can't wait for an NMI
733 * to reset an overflowed counter value.
734 */
735 if (in_nmi())
736 return;
737
738 /*
739 * Check each counter for overflow and wait for it to be reset by the
740 * NMI if it has overflowed. This relies on the fact that all active
741 * counters are always enabled when this function is called and
742 * ARCH_PERFMON_EVENTSEL_INT is always set.
743 */
744 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
745 if (!test_bit(idx, cpuc->active_mask))
746 continue;
747
748 amd_pmu_wait_on_overflow(idx);
749 }
750 }
751
amd_pmu_enable_event(struct perf_event * event)752 static void amd_pmu_enable_event(struct perf_event *event)
753 {
754 x86_pmu_enable_event(event);
755 }
756
__amd_pmu_enable_all(void)757 static void __amd_pmu_enable_all(void)
758 {
759 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
760 int idx;
761
762 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
763 /* only activate events which are marked as active */
764 if (!test_bit(idx, cpuc->active_mask))
765 continue;
766
767 /*
768 * FIXME: cpuc->events[idx] can become NULL in a subtle race
769 * condition with NMI->throttle->x86_pmu_stop().
770 */
771 if (cpuc->events[idx])
772 amd_pmu_enable_event(cpuc->events[idx]);
773 }
774 }
775
amd_pmu_enable_all(int added)776 static void amd_pmu_enable_all(int added)
777 {
778 amd_brs_enable_all();
779 __amd_pmu_enable_all();
780 }
781
amd_pmu_v2_enable_event(struct perf_event * event)782 static void amd_pmu_v2_enable_event(struct perf_event *event)
783 {
784 struct hw_perf_event *hwc = &event->hw;
785
786 /*
787 * Testing cpu_hw_events.enabled should be skipped in this case unlike
788 * in x86_pmu_enable_event().
789 *
790 * Since cpu_hw_events.enabled is set only after returning from
791 * x86_pmu_start(), the PMCs must be programmed and kept ready.
792 * Counting starts only after x86_pmu_enable_all() is called.
793 */
794 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
795 }
796
amd_pmu_core_enable_all(void)797 static __always_inline void amd_pmu_core_enable_all(void)
798 {
799 amd_pmu_set_global_ctl(amd_pmu_global_cntr_mask);
800 }
801
amd_pmu_v2_enable_all(int added)802 static void amd_pmu_v2_enable_all(int added)
803 {
804 amd_pmu_lbr_enable_all();
805 amd_pmu_core_enable_all();
806 }
807
amd_pmu_disable_event(struct perf_event * event)808 static void amd_pmu_disable_event(struct perf_event *event)
809 {
810 x86_pmu_disable_event(event);
811
812 /*
813 * This can be called from NMI context (via x86_pmu_stop). The counter
814 * may have overflowed, but either way, we'll never see it get reset
815 * by the NMI if we're already in the NMI. And the NMI latency support
816 * below will take care of any pending NMI that might have been
817 * generated by the overflow.
818 */
819 if (in_nmi())
820 return;
821
822 amd_pmu_wait_on_overflow(event->hw.idx);
823 }
824
amd_pmu_disable_all(void)825 static void amd_pmu_disable_all(void)
826 {
827 amd_brs_disable_all();
828 x86_pmu_disable_all();
829 amd_pmu_check_overflow();
830 }
831
amd_pmu_core_disable_all(void)832 static __always_inline void amd_pmu_core_disable_all(void)
833 {
834 amd_pmu_set_global_ctl(0);
835 }
836
amd_pmu_v2_disable_all(void)837 static void amd_pmu_v2_disable_all(void)
838 {
839 amd_pmu_core_disable_all();
840 amd_pmu_lbr_disable_all();
841 amd_pmu_check_overflow();
842 }
843
844 DEFINE_STATIC_CALL_NULL(amd_pmu_branch_add, *x86_pmu.add);
845
amd_pmu_add_event(struct perf_event * event)846 static void amd_pmu_add_event(struct perf_event *event)
847 {
848 if (needs_branch_stack(event))
849 static_call(amd_pmu_branch_add)(event);
850 }
851
852 DEFINE_STATIC_CALL_NULL(amd_pmu_branch_del, *x86_pmu.del);
853
amd_pmu_del_event(struct perf_event * event)854 static void amd_pmu_del_event(struct perf_event *event)
855 {
856 if (needs_branch_stack(event))
857 static_call(amd_pmu_branch_del)(event);
858 }
859
860 /*
861 * Because of NMI latency, if multiple PMC counters are active or other sources
862 * of NMIs are received, the perf NMI handler can handle one or more overflowed
863 * PMC counters outside of the NMI associated with the PMC overflow. If the NMI
864 * doesn't arrive at the LAPIC in time to become a pending NMI, then the kernel
865 * back-to-back NMI support won't be active. This PMC handler needs to take into
866 * account that this can occur, otherwise this could result in unknown NMI
867 * messages being issued. Examples of this is PMC overflow while in the NMI
868 * handler when multiple PMCs are active or PMC overflow while handling some
869 * other source of an NMI.
870 *
871 * Attempt to mitigate this by creating an NMI window in which un-handled NMIs
872 * received during this window will be claimed. This prevents extending the
873 * window past when it is possible that latent NMIs should be received. The
874 * per-CPU perf_nmi_tstamp will be set to the window end time whenever perf has
875 * handled a counter. When an un-handled NMI is received, it will be claimed
876 * only if arriving within that window.
877 */
amd_pmu_adjust_nmi_window(int handled)878 static inline int amd_pmu_adjust_nmi_window(int handled)
879 {
880 /*
881 * If a counter was handled, record a timestamp such that un-handled
882 * NMIs will be claimed if arriving within that window.
883 */
884 if (handled) {
885 this_cpu_write(perf_nmi_tstamp, jiffies + perf_nmi_window);
886
887 return handled;
888 }
889
890 if (time_after(jiffies, this_cpu_read(perf_nmi_tstamp)))
891 return NMI_DONE;
892
893 return NMI_HANDLED;
894 }
895
amd_pmu_handle_irq(struct pt_regs * regs)896 static int amd_pmu_handle_irq(struct pt_regs *regs)
897 {
898 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
899 int handled;
900 int pmu_enabled;
901
902 /*
903 * Save the PMU state.
904 * It needs to be restored when leaving the handler.
905 */
906 pmu_enabled = cpuc->enabled;
907 cpuc->enabled = 0;
908
909 amd_brs_disable_all();
910
911 /* Drain BRS is in use (could be inactive) */
912 if (cpuc->lbr_users)
913 amd_brs_drain();
914
915 /* Process any counter overflows */
916 handled = x86_pmu_handle_irq(regs);
917
918 cpuc->enabled = pmu_enabled;
919 if (pmu_enabled)
920 amd_brs_enable_all();
921
922 return amd_pmu_adjust_nmi_window(handled);
923 }
924
925 /*
926 * AMD-specific callback invoked through perf_snapshot_branch_stack static
927 * call, defined in include/linux/perf_event.h. See its definition for API
928 * details. It's up to caller to provide enough space in *entries* to fit all
929 * LBR records, otherwise returned result will be truncated to *cnt* entries.
930 */
amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)931 static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
932 {
933 struct cpu_hw_events *cpuc;
934 unsigned long flags;
935
936 /*
937 * The sequence of steps to freeze LBR should be completely inlined
938 * and contain no branches to minimize contamination of LBR snapshot
939 */
940 local_irq_save(flags);
941 amd_pmu_core_disable_all();
942 __amd_pmu_lbr_disable();
943
944 cpuc = this_cpu_ptr(&cpu_hw_events);
945
946 amd_pmu_lbr_read();
947 cnt = min(cnt, x86_pmu.lbr_nr);
948 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
949
950 amd_pmu_v2_enable_all(0);
951 local_irq_restore(flags);
952
953 return cnt;
954 }
955
amd_pmu_v2_handle_irq(struct pt_regs * regs)956 static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
957 {
958 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
959 static atomic64_t status_warned = ATOMIC64_INIT(0);
960 u64 reserved, status, mask, new_bits, prev_bits;
961 struct perf_sample_data data;
962 struct hw_perf_event *hwc;
963 struct perf_event *event;
964 int handled = 0, idx;
965 bool pmu_enabled;
966
967 /*
968 * Save the PMU state as it needs to be restored when leaving the
969 * handler
970 */
971 pmu_enabled = cpuc->enabled;
972 cpuc->enabled = 0;
973
974 /* Stop counting but do not disable LBR */
975 amd_pmu_core_disable_all();
976
977 status = amd_pmu_get_global_status();
978
979 /* Check if any overflows are pending */
980 if (!status)
981 goto done;
982
983 /* Read branch records */
984 if (x86_pmu.lbr_nr) {
985 amd_pmu_lbr_read();
986 status &= ~GLOBAL_STATUS_LBRS_FROZEN;
987 }
988
989 reserved = status & ~amd_pmu_global_cntr_mask;
990 if (reserved)
991 pr_warn_once("Reserved PerfCntrGlobalStatus bits are set (0x%llx), please consider updating microcode\n",
992 reserved);
993
994 /* Clear any reserved bits set by buggy microcode */
995 status &= amd_pmu_global_cntr_mask;
996
997 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
998 if (!test_bit(idx, cpuc->active_mask))
999 continue;
1000
1001 event = cpuc->events[idx];
1002 hwc = &event->hw;
1003 x86_perf_event_update(event);
1004 mask = BIT_ULL(idx);
1005
1006 if (!(status & mask))
1007 continue;
1008
1009 /* Event overflow */
1010 handled++;
1011 status &= ~mask;
1012 perf_sample_data_init(&data, 0, hwc->last_period);
1013
1014 if (!x86_perf_event_set_period(event))
1015 continue;
1016
1017 perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL);
1018
1019 perf_event_overflow(event, &data, regs);
1020 }
1021
1022 /*
1023 * It should never be the case that some overflows are not handled as
1024 * the corresponding PMCs are expected to be inactive according to the
1025 * active_mask
1026 */
1027 if (status > 0) {
1028 prev_bits = atomic64_fetch_or(status, &status_warned);
1029 // A new bit was set for the very first time.
1030 new_bits = status & ~prev_bits;
1031 WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
1032 }
1033
1034 /* Clear overflow and freeze bits */
1035 amd_pmu_ack_global_status(~status);
1036
1037 /*
1038 * Unmasking the LVTPC is not required as the Mask (M) bit of the LVT
1039 * PMI entry is not set by the local APIC when a PMC overflow occurs
1040 */
1041 inc_perf_irq_stat();
1042
1043 done:
1044 cpuc->enabled = pmu_enabled;
1045
1046 /* Resume counting only if PMU is active */
1047 if (pmu_enabled)
1048 amd_pmu_core_enable_all();
1049
1050 return amd_pmu_adjust_nmi_window(handled);
1051 }
1052
1053 static struct event_constraint *
amd_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)1054 amd_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1055 struct perf_event *event)
1056 {
1057 /*
1058 * if not NB event or no NB, then no constraints
1059 */
1060 if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
1061 return &unconstrained;
1062
1063 return __amd_get_nb_event_constraints(cpuc, event, NULL);
1064 }
1065
amd_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)1066 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
1067 struct perf_event *event)
1068 {
1069 if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
1070 __amd_put_nb_event_constraints(cpuc, event);
1071 }
1072
1073 PMU_FORMAT_ATTR(event, "config:0-7,32-35");
1074 PMU_FORMAT_ATTR(umask, "config:8-15" );
1075 PMU_FORMAT_ATTR(edge, "config:18" );
1076 PMU_FORMAT_ATTR(inv, "config:23" );
1077 PMU_FORMAT_ATTR(cmask, "config:24-31" );
1078
1079 static struct attribute *amd_format_attr[] = {
1080 &format_attr_event.attr,
1081 &format_attr_umask.attr,
1082 &format_attr_edge.attr,
1083 &format_attr_inv.attr,
1084 &format_attr_cmask.attr,
1085 NULL,
1086 };
1087
1088 /* AMD Family 15h */
1089
1090 #define AMD_EVENT_TYPE_MASK 0x000000F0ULL
1091
1092 #define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL
1093 #define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL
1094 #define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL
1095 #define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL
1096 #define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL
1097 #define AMD_EVENT_EX_LS 0x000000C0ULL
1098 #define AMD_EVENT_DE 0x000000D0ULL
1099 #define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL
1100
1101 /*
1102 * AMD family 15h event code/PMC mappings:
1103 *
1104 * type = event_code & 0x0F0:
1105 *
1106 * 0x000 FP PERF_CTL[5:3]
1107 * 0x010 FP PERF_CTL[5:3]
1108 * 0x020 LS PERF_CTL[5:0]
1109 * 0x030 LS PERF_CTL[5:0]
1110 * 0x040 DC PERF_CTL[5:0]
1111 * 0x050 DC PERF_CTL[5:0]
1112 * 0x060 CU PERF_CTL[2:0]
1113 * 0x070 CU PERF_CTL[2:0]
1114 * 0x080 IC/DE PERF_CTL[2:0]
1115 * 0x090 IC/DE PERF_CTL[2:0]
1116 * 0x0A0 ---
1117 * 0x0B0 ---
1118 * 0x0C0 EX/LS PERF_CTL[5:0]
1119 * 0x0D0 DE PERF_CTL[2:0]
1120 * 0x0E0 NB NB_PERF_CTL[3:0]
1121 * 0x0F0 NB NB_PERF_CTL[3:0]
1122 *
1123 * Exceptions:
1124 *
1125 * 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
1126 * 0x003 FP PERF_CTL[3]
1127 * 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
1128 * 0x00B FP PERF_CTL[3]
1129 * 0x00D FP PERF_CTL[3]
1130 * 0x023 DE PERF_CTL[2:0]
1131 * 0x02D LS PERF_CTL[3]
1132 * 0x02E LS PERF_CTL[3,0]
1133 * 0x031 LS PERF_CTL[2:0] (**)
1134 * 0x043 CU PERF_CTL[2:0]
1135 * 0x045 CU PERF_CTL[2:0]
1136 * 0x046 CU PERF_CTL[2:0]
1137 * 0x054 CU PERF_CTL[2:0]
1138 * 0x055 CU PERF_CTL[2:0]
1139 * 0x08F IC PERF_CTL[0]
1140 * 0x187 DE PERF_CTL[0]
1141 * 0x188 DE PERF_CTL[0]
1142 * 0x0DB EX PERF_CTL[5:0]
1143 * 0x0DC LS PERF_CTL[5:0]
1144 * 0x0DD LS PERF_CTL[5:0]
1145 * 0x0DE LS PERF_CTL[5:0]
1146 * 0x0DF LS PERF_CTL[5:0]
1147 * 0x1C0 EX PERF_CTL[5:3]
1148 * 0x1D6 EX PERF_CTL[5:0]
1149 * 0x1D8 EX PERF_CTL[5:0]
1150 *
1151 * (*) depending on the umask all FPU counters may be used
1152 * (**) only one unitmask enabled at a time
1153 */
1154
1155 static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0);
1156 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
1157 static struct event_constraint amd_f15_PMC3 = EVENT_CONSTRAINT(0, 0x08, 0);
1158 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
1159 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
1160 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
1161
1162 static struct event_constraint *
amd_get_event_constraints_f15h(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)1163 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, int idx,
1164 struct perf_event *event)
1165 {
1166 struct hw_perf_event *hwc = &event->hw;
1167 unsigned int event_code = amd_get_event_code(hwc);
1168
1169 switch (event_code & AMD_EVENT_TYPE_MASK) {
1170 case AMD_EVENT_FP:
1171 switch (event_code) {
1172 case 0x000:
1173 if (!(hwc->config & 0x0000F000ULL))
1174 break;
1175 if (!(hwc->config & 0x00000F00ULL))
1176 break;
1177 return &amd_f15_PMC3;
1178 case 0x004:
1179 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
1180 break;
1181 return &amd_f15_PMC3;
1182 case 0x003:
1183 case 0x00B:
1184 case 0x00D:
1185 return &amd_f15_PMC3;
1186 }
1187 return &amd_f15_PMC53;
1188 case AMD_EVENT_LS:
1189 case AMD_EVENT_DC:
1190 case AMD_EVENT_EX_LS:
1191 switch (event_code) {
1192 case 0x023:
1193 case 0x043:
1194 case 0x045:
1195 case 0x046:
1196 case 0x054:
1197 case 0x055:
1198 return &amd_f15_PMC20;
1199 case 0x02D:
1200 return &amd_f15_PMC3;
1201 case 0x02E:
1202 return &amd_f15_PMC30;
1203 case 0x031:
1204 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
1205 return &amd_f15_PMC20;
1206 return &emptyconstraint;
1207 case 0x1C0:
1208 return &amd_f15_PMC53;
1209 default:
1210 return &amd_f15_PMC50;
1211 }
1212 case AMD_EVENT_CU:
1213 case AMD_EVENT_IC_DE:
1214 case AMD_EVENT_DE:
1215 switch (event_code) {
1216 case 0x08F:
1217 case 0x187:
1218 case 0x188:
1219 return &amd_f15_PMC0;
1220 case 0x0DB ... 0x0DF:
1221 case 0x1D6:
1222 case 0x1D8:
1223 return &amd_f15_PMC50;
1224 default:
1225 return &amd_f15_PMC20;
1226 }
1227 case AMD_EVENT_NB:
1228 /* moved to uncore.c */
1229 return &emptyconstraint;
1230 default:
1231 return &emptyconstraint;
1232 }
1233 }
1234
1235 static struct event_constraint pair_constraint;
1236
1237 static struct event_constraint *
amd_get_event_constraints_f17h(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)1238 amd_get_event_constraints_f17h(struct cpu_hw_events *cpuc, int idx,
1239 struct perf_event *event)
1240 {
1241 struct hw_perf_event *hwc = &event->hw;
1242
1243 if (amd_is_pair_event_code(hwc))
1244 return &pair_constraint;
1245
1246 return &unconstrained;
1247 }
1248
amd_put_event_constraints_f17h(struct cpu_hw_events * cpuc,struct perf_event * event)1249 static void amd_put_event_constraints_f17h(struct cpu_hw_events *cpuc,
1250 struct perf_event *event)
1251 {
1252 struct hw_perf_event *hwc = &event->hw;
1253
1254 if (is_counter_pair(hwc))
1255 --cpuc->n_pair;
1256 }
1257
1258 /*
1259 * Because of the way BRS operates with an inactive and active phases, and
1260 * the link to one counter, it is not possible to have two events using BRS
1261 * scheduled at the same time. There would be an issue with enforcing the
1262 * period of each one and given that the BRS saturates, it would not be possible
1263 * to guarantee correlated content for all events. Therefore, in situations
1264 * where multiple events want to use BRS, the kernel enforces mutual exclusion.
1265 * Exclusion is enforced by choosing only one counter for events using BRS.
1266 * The event scheduling logic will then automatically multiplex the
1267 * events and ensure that at most one event is actively using BRS.
1268 *
1269 * The BRS counter could be any counter, but there is no constraint on Fam19h,
1270 * therefore all counters are equal and thus we pick the first one: PMC0
1271 */
1272 static struct event_constraint amd_fam19h_brs_cntr0_constraint =
1273 EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK);
1274
1275 static struct event_constraint amd_fam19h_brs_pair_cntr0_constraint =
1276 __EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK, 1, 0, PERF_X86_EVENT_PAIR);
1277
1278 static struct event_constraint *
amd_get_event_constraints_f19h(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)1279 amd_get_event_constraints_f19h(struct cpu_hw_events *cpuc, int idx,
1280 struct perf_event *event)
1281 {
1282 struct hw_perf_event *hwc = &event->hw;
1283 bool has_brs = has_amd_brs(hwc);
1284
1285 /*
1286 * In case BRS is used with an event requiring a counter pair,
1287 * the kernel allows it but only on counter 0 & 1 to enforce
1288 * multiplexing requiring to protect BRS in case of multiple
1289 * BRS users
1290 */
1291 if (amd_is_pair_event_code(hwc)) {
1292 return has_brs ? &amd_fam19h_brs_pair_cntr0_constraint
1293 : &pair_constraint;
1294 }
1295
1296 if (has_brs)
1297 return &amd_fam19h_brs_cntr0_constraint;
1298
1299 return &unconstrained;
1300 }
1301
1302
amd_event_sysfs_show(char * page,u64 config)1303 static ssize_t amd_event_sysfs_show(char *page, u64 config)
1304 {
1305 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) |
1306 (config & AMD64_EVENTSEL_EVENT) >> 24;
1307
1308 return x86_event_sysfs_show(page, config, event);
1309 }
1310
amd_pmu_limit_period(struct perf_event * event,s64 * left)1311 static void amd_pmu_limit_period(struct perf_event *event, s64 *left)
1312 {
1313 /*
1314 * Decrease period by the depth of the BRS feature to get the last N
1315 * taken branches and approximate the desired period
1316 */
1317 if (has_branch_stack(event) && *left > x86_pmu.lbr_nr)
1318 *left -= x86_pmu.lbr_nr;
1319 }
1320
1321 static __initconst const struct x86_pmu amd_pmu = {
1322 .name = "AMD",
1323 .handle_irq = amd_pmu_handle_irq,
1324 .disable_all = amd_pmu_disable_all,
1325 .enable_all = amd_pmu_enable_all,
1326 .enable = amd_pmu_enable_event,
1327 .disable = amd_pmu_disable_event,
1328 .hw_config = amd_pmu_hw_config,
1329 .schedule_events = x86_schedule_events,
1330 .eventsel = MSR_K7_EVNTSEL0,
1331 .perfctr = MSR_K7_PERFCTR0,
1332 .addr_offset = amd_pmu_addr_offset,
1333 .event_map = amd_pmu_event_map,
1334 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
1335 .cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS - 1, 0),
1336 .add = amd_pmu_add_event,
1337 .del = amd_pmu_del_event,
1338 .cntval_bits = 48,
1339 .cntval_mask = (1ULL << 48) - 1,
1340 .apic = 1,
1341 /* use highest bit to detect overflow */
1342 .max_period = (1ULL << 47) - 1,
1343 .get_event_constraints = amd_get_event_constraints,
1344 .put_event_constraints = amd_put_event_constraints,
1345
1346 .format_attrs = amd_format_attr,
1347 .events_sysfs_show = amd_event_sysfs_show,
1348
1349 .cpu_prepare = amd_pmu_cpu_prepare,
1350 .cpu_starting = amd_pmu_cpu_starting,
1351 .cpu_dead = amd_pmu_cpu_dead,
1352
1353 .amd_nb_constraints = 1,
1354 };
1355
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)1356 static ssize_t branches_show(struct device *cdev,
1357 struct device_attribute *attr,
1358 char *buf)
1359 {
1360 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
1361 }
1362
1363 static DEVICE_ATTR_RO(branches);
1364
1365 static struct attribute *amd_pmu_branches_attrs[] = {
1366 &dev_attr_branches.attr,
1367 NULL,
1368 };
1369
1370 static umode_t
amd_branches_is_visible(struct kobject * kobj,struct attribute * attr,int i)1371 amd_branches_is_visible(struct kobject *kobj, struct attribute *attr, int i)
1372 {
1373 return x86_pmu.lbr_nr ? attr->mode : 0;
1374 }
1375
1376 static struct attribute_group group_caps_amd_branches = {
1377 .name = "caps",
1378 .attrs = amd_pmu_branches_attrs,
1379 .is_visible = amd_branches_is_visible,
1380 };
1381
1382 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1383
1384 EVENT_ATTR_STR(branch-brs, amd_branch_brs,
1385 "event=" __stringify(AMD_FAM19H_BRS_EVENT)"\n");
1386
1387 static struct attribute *amd_brs_events_attrs[] = {
1388 EVENT_PTR(amd_branch_brs),
1389 NULL,
1390 };
1391
1392 static umode_t
amd_brs_is_visible(struct kobject * kobj,struct attribute * attr,int i)1393 amd_brs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
1394 {
1395 return cpu_feature_enabled(X86_FEATURE_BRS) && x86_pmu.lbr_nr ?
1396 attr->mode : 0;
1397 }
1398
1399 static struct attribute_group group_events_amd_brs = {
1400 .name = "events",
1401 .attrs = amd_brs_events_attrs,
1402 .is_visible = amd_brs_is_visible,
1403 };
1404
1405 #endif /* CONFIG_PERF_EVENTS_AMD_BRS */
1406
1407 static const struct attribute_group *amd_attr_update[] = {
1408 &group_caps_amd_branches,
1409 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1410 &group_events_amd_brs,
1411 #endif
1412 NULL,
1413 };
1414
amd_core_pmu_init(void)1415 static int __init amd_core_pmu_init(void)
1416 {
1417 union cpuid_0x80000022_ebx ebx;
1418 u64 even_ctr_mask = 0ULL;
1419 int i;
1420
1421 /* Avoid calculating the value each time in the NMI handler */
1422 perf_nmi_window = msecs_to_jiffies(100);
1423
1424 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
1425 return 0;
1426
1427 /*
1428 * If core performance counter extensions exists, we must use
1429 * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
1430 * amd_pmu_addr_offset().
1431 */
1432 x86_pmu.eventsel = MSR_F15H_PERF_CTL;
1433 x86_pmu.perfctr = MSR_F15H_PERF_CTR;
1434 x86_pmu.cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS_CORE - 1, 0);
1435
1436 /* Check for Performance Monitoring v2 support */
1437 if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) {
1438 ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
1439
1440 /* Update PMU version for later usage */
1441 x86_pmu.version = 2;
1442
1443 /* Find the number of available Core PMCs */
1444 x86_pmu.cntr_mask64 = GENMASK_ULL(ebx.split.num_core_pmc - 1, 0);
1445
1446 amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64;
1447
1448 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
1449
1450 /* Update PMC handling functions */
1451 x86_pmu.enable_all = amd_pmu_v2_enable_all;
1452 x86_pmu.disable_all = amd_pmu_v2_disable_all;
1453 x86_pmu.enable = amd_pmu_v2_enable_event;
1454 x86_pmu.handle_irq = amd_pmu_v2_handle_irq;
1455 static_call_update(amd_pmu_test_overflow, amd_pmu_test_overflow_status);
1456 }
1457
1458 /*
1459 * AMD Core perfctr has separate MSRs for the NB events, see
1460 * the amd/uncore.c driver.
1461 */
1462 x86_pmu.amd_nb_constraints = 0;
1463
1464 if (boot_cpu_data.x86 == 0x15) {
1465 pr_cont("Fam15h ");
1466 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
1467 }
1468 if (boot_cpu_data.x86 >= 0x17) {
1469 pr_cont("Fam17h+ ");
1470 /*
1471 * Family 17h and compatibles have constraints for Large
1472 * Increment per Cycle events: they may only be assigned an
1473 * even numbered counter that has a consecutive adjacent odd
1474 * numbered counter following it.
1475 */
1476 for (i = 0; i < x86_pmu_max_num_counters(NULL) - 1; i += 2)
1477 even_ctr_mask |= BIT_ULL(i);
1478
1479 pair_constraint = (struct event_constraint)
1480 __EVENT_CONSTRAINT(0, even_ctr_mask, 0,
1481 x86_pmu_max_num_counters(NULL) / 2, 0,
1482 PERF_X86_EVENT_PAIR);
1483
1484 x86_pmu.get_event_constraints = amd_get_event_constraints_f17h;
1485 x86_pmu.put_event_constraints = amd_put_event_constraints_f17h;
1486 x86_pmu.perf_ctr_pair_en = AMD_MERGE_EVENT_ENABLE;
1487 x86_pmu.flags |= PMU_FL_PAIR;
1488 }
1489
1490 /* LBR and BRS are mutually exclusive features */
1491 if (!amd_pmu_lbr_init()) {
1492 /* LBR requires flushing on context switch */
1493 x86_pmu.sched_task = amd_pmu_lbr_sched_task;
1494 static_call_update(amd_pmu_branch_hw_config, amd_pmu_lbr_hw_config);
1495 static_call_update(amd_pmu_branch_reset, amd_pmu_lbr_reset);
1496 static_call_update(amd_pmu_branch_add, amd_pmu_lbr_add);
1497 static_call_update(amd_pmu_branch_del, amd_pmu_lbr_del);
1498
1499 /* Only support branch_stack snapshot on perfmon v2 */
1500 if (x86_pmu.handle_irq == amd_pmu_v2_handle_irq)
1501 static_call_update(perf_snapshot_branch_stack, amd_pmu_v2_snapshot_branch_stack);
1502 } else if (!amd_brs_init()) {
1503 /*
1504 * BRS requires special event constraints and flushing on ctxsw.
1505 */
1506 x86_pmu.get_event_constraints = amd_get_event_constraints_f19h;
1507 x86_pmu.sched_task = amd_pmu_brs_sched_task;
1508 x86_pmu.limit_period = amd_pmu_limit_period;
1509
1510 static_call_update(amd_pmu_branch_hw_config, amd_brs_hw_config);
1511 static_call_update(amd_pmu_branch_reset, amd_brs_reset);
1512 static_call_update(amd_pmu_branch_add, amd_pmu_brs_add);
1513 static_call_update(amd_pmu_branch_del, amd_pmu_brs_del);
1514
1515 /*
1516 * put_event_constraints callback same as Fam17h, set above
1517 */
1518
1519 /* branch sampling must be stopped when entering low power */
1520 amd_brs_lopwr_init();
1521 }
1522
1523 x86_pmu.attr_update = amd_attr_update;
1524
1525 pr_cont("core perfctr, ");
1526 return 0;
1527 }
1528
amd_pmu_init(void)1529 __init int amd_pmu_init(void)
1530 {
1531 int ret;
1532
1533 /* Performance-monitoring supported from K7 and later: */
1534 if (boot_cpu_data.x86 < 6)
1535 return -ENODEV;
1536
1537 x86_pmu = amd_pmu;
1538
1539 ret = amd_core_pmu_init();
1540 if (ret)
1541 return ret;
1542
1543 if (num_possible_cpus() == 1) {
1544 /*
1545 * No point in allocating data structures to serialize
1546 * against other CPUs, when there is only the one CPU.
1547 */
1548 x86_pmu.amd_nb_constraints = 0;
1549 }
1550
1551 if (boot_cpu_data.x86 >= 0x17)
1552 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids_f17h, sizeof(hw_cache_event_ids));
1553 else
1554 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, sizeof(hw_cache_event_ids));
1555
1556 return 0;
1557 }
1558
amd_pmu_reload_virt(void)1559 static inline void amd_pmu_reload_virt(void)
1560 {
1561 if (x86_pmu.version >= 2) {
1562 /*
1563 * Clear global enable bits, reprogram the PERF_CTL
1564 * registers with updated perf_ctr_virt_mask and then
1565 * set global enable bits once again
1566 */
1567 amd_pmu_v2_disable_all();
1568 __amd_pmu_enable_all();
1569 amd_pmu_v2_enable_all(0);
1570 return;
1571 }
1572
1573 amd_pmu_disable_all();
1574 amd_pmu_enable_all(0);
1575 }
1576
amd_pmu_enable_virt(void)1577 void amd_pmu_enable_virt(void)
1578 {
1579 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1580
1581 cpuc->perf_ctr_virt_mask = 0;
1582
1583 /* Reload all events */
1584 amd_pmu_reload_virt();
1585 }
1586 EXPORT_SYMBOL_FOR_KVM(amd_pmu_enable_virt);
1587
amd_pmu_disable_virt(void)1588 void amd_pmu_disable_virt(void)
1589 {
1590 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1591
1592 /*
1593 * We only mask out the Host-only bit so that host-only counting works
1594 * when SVM is disabled. If someone sets up a guest-only counter when
1595 * SVM is disabled the Guest-only bits still gets set and the counter
1596 * will not count anything.
1597 */
1598 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
1599
1600 /* Reload all events */
1601 amd_pmu_reload_virt();
1602 }
1603 EXPORT_SYMBOL_FOR_KVM(amd_pmu_disable_virt);
1604