| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 65 uint32_t alpha_en = 1; in dpp401_dpp_setup() local
94 alpha_en = 0; in dpp401_dpp_setup()
142 alpha_en = 0; in dpp401_dpp_setup()
146 alpha_en = 0; in dpp401_dpp_setup()
170 alpha_en = 0; in dpp401_dpp_setup()
174 alpha_en = 0; in dpp401_dpp_setup()
193 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp401_dpp_setup()
346 if (scl_data->lb_params.alpha_en in dscl401_calc_lb_num_partitions()
358 bool alpha_en, in dscl401_spl_calc_lb_num_partitions() argument
421 if (alpha_en && (num_partitions_a < *num_part_y)) in dscl401_spl_calc_lb_num_partitions()
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| H A D | dcn401_dpp_dscl.c | 201 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp401_dscl_set_lb()
206 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp401_dscl_set_lb()
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| H A D | dcn401_dpp.h | 716 bool alpha_en,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.c | 107 uint32_t alpha_en = 1; in dpp2_cnv_setup() local
135 alpha_en = 0; in dpp2_cnv_setup()
187 alpha_en = 0; in dpp2_cnv_setup()
191 alpha_en = 0; in dpp2_cnv_setup()
207 alpha_en = 0; in dpp2_cnv_setup()
211 alpha_en = 0; in dpp2_cnv_setup()
229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
306 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
437 bool alpha_en, in dscl2_spl_calc_lb_num_partitions() argument
483 if (alpha_en in dscl2_spl_calc_lb_num_partitions()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 54 uint32_t alpha_en = 1; in dpp201_cnv_setup() local
82 alpha_en = 0; in dpp201_cnv_setup()
133 alpha_en = 0; in dpp201_cnv_setup()
137 alpha_en = 0; in dpp201_cnv_setup()
153 alpha_en = 0; in dpp201_cnv_setup()
157 alpha_en = 0; in dpp201_cnv_setup()
175 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/ |
| H A D | dcn32_dpp.c | 97 if (scl_data->lb_params.alpha_en in dscl32_calc_lb_num_partitions()
167 bool alpha_en, in dscl32_spl_calc_lb_num_partitions() argument
230 if (alpha_en in dscl32_spl_calc_lb_num_partitions()
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| H A D | dcn32_dpp.h | 40 bool alpha_en,
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| /linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop_reg.c | 131 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
149 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
219 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
321 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
338 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
355 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
420 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0),
439 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1),
454 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2),
545 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0),
[all …]
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| H A D | rockchip_drm_vop.h | 207 struct vop_reg alpha_en; member
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| H A D | rockchip_drm_vop.c | 1063 VOP_WIN_SET(vop, win, alpha_en, 1); in vop_plane_atomic_update()
1066 VOP_WIN_SET(vop, win, alpha_en, 0); in vop_plane_atomic_update()
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| H A D | rockchip_drm_vop2.c | 116 u32 alpha_en:1; member
2109 alpha->src_color_ctrl.bits.alpha_en = 1; in vop2_parse_alpha()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp.c | 283 uint32_t alpha_en; in dpp1_cnv_setup() local
294 alpha_en = 1; in dpp1_cnv_setup()
329 alpha_en = 0; in dpp1_cnv_setup()
382 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
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| H A D | dcn10_dpp_dscl.c | 199 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
204 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
439 if (scl_data->lb_params.alpha_en in dpp1_dscl_calc_lb_num_partitions()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.c | 214 uint32_t alpha_en = 1; in dpp3_cnv_setup() local
244 alpha_en = 0; in dpp3_cnv_setup()
296 alpha_en = 0; in dpp3_cnv_setup()
300 alpha_en = 0; in dpp3_cnv_setup()
324 alpha_en = 0; in dpp3_cnv_setup()
328 alpha_en = 0; in dpp3_cnv_setup()
347 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/spl/ |
| H A D | dc_spl_types.h | 460 bool alpha_en; member
502 (bool alpha_en,
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | transform.h | 139 bool alpha_en; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_transform.c | 486 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); in dce_transform_set_scaler()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1693 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2918 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 2758 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
|