Searched refs:allowed_sclk_vddc_table (Results 1 – 2 of 2) sorted by relevance
3404 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_setup_default_dpm_tables() local3412 if (allowed_sclk_vddc_table->count < 1) in ci_setup_default_dpm_tables()3436 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3439 allowed_sclk_vddc_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3441 allowed_sclk_vddc_table->entries[i].clk; in ci_setup_default_dpm_tables()3461 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3463 allowed_sclk_vddc_table->entries[i].v; in ci_setup_default_dpm_tables()3468 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()4873 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_set_private_data_variables_based_on_pptable() local4880 if (allowed_sclk_vddc_table->count < 1) in ci_set_private_data_variables_based_on_pptable()[all …]
2847 …struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_depende… in smu7_set_private_data_based_on_pptable_v0() local2851 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, in smu7_set_private_data_based_on_pptable_v0()2854 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, in smu7_set_private_data_based_on_pptable_v0()2865 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; in smu7_set_private_data_based_on_pptable_v0()2866 …data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->co… in smu7_set_private_data_based_on_pptable_v0()2869 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v0()2873 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; in smu7_set_private_data_based_on_pptable_v0()