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Searched refs:ack_irq (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/mailbox/
H A Dhi6220-mailbox.c62 unsigned int dir, dst_irq, ack_irq; member
187 writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); in hi6220_mbox_interrupt()
202 writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); in hi6220_mbox_startup()
212 writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); in hi6220_mbox_shutdown()
213 mbox->irq_map_chan[mchan->ack_irq] = NULL; in hi6220_mbox_shutdown()
231 unsigned int ack_irq = spec->args[2]; in hi6220_mbox_xlate() local
235 ack_irq >= mbox->chan_num) { in hi6220_mbox_xlate()
238 i, dst_irq, ack_irq); in hi6220_mbox_xlate()
244 if (mbox->irq_map_chan[ack_irq] == (void *)chan) { in hi6220_mbox_xlate()
251 mchan->ack_irq = ack_irq; in hi6220_mbox_xlate()
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H A Dhi3660-mailbox.c58 unsigned int ack_irq; member
107 writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG); in hi3660_mbox_check_state()
144 writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); in hi3660_mbox_acquire_channel()
148 if (val & BIT(mchan->ack_irq)) in hi3660_mbox_acquire_channel()
202 writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG); in hi3660_mbox_send_data()
225 mchan->ack_irq = spec->args[2]; in hi3660_mbox_xlate()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c353 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
354 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
367 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
383 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
396 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
H A Dmxgpu_vi.c580 adev->virt.ack_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
581 adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs; in xgpu_vi_mailbox_set_irq_funcs()
594 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); in xgpu_vi_mailbox_add_irq_id()
610 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_get_irq()
623 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_put_irq()
H A Damdgpu_virt.h252 struct amdgpu_irq_src ack_irq; member
/linux/Documentation/devicetree/bindings/mailbox/
H A Dhisilicon,hi3660-mailbox.txt15 <&phandle channel dst_irq ack_irq>
19 ack_irq : Local interrupt vector
H A Dhisilicon,hi6220-mailbox.txt21 <&phandle slot_id dst_irq ack_irq>
25 ack_irq: IRQ identifier index number with generating a
/linux/drivers/misc/ocxl/
H A Dlink.c118 static void ack_irq(struct spa *spa, enum xsl_response r) in ack_irq() function
186 ack_irq(spa, r); in xsl_fault_handler_bh()
214 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
233 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
244 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
261 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
/linux/drivers/misc/cxl/
H A Dfault.c101 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_AE, 0); in cxl_ack_ae()
125 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); in cxl_handle_segment_miss()
190 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); in cxl_handle_page_fault()
H A Dirq.c75 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); in cxl_irq_psl9()
161 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); in cxl_irq_psl8()
H A Dguest.c67 return cxl_ops->ack_irq(ctx, 0, errstat); in guest_handle_psl_slice_error()
1188 .ack_irq = guest_ack_irq,
H A Dnative.c1145 return cxl_ops->ack_irq(ctx, 0, errstat); in native_handle_psl_slice_error()
1571 .ack_irq = native_ack_irq,
H A Dcxl.h1080 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask); member
/linux/drivers/media/pci/cx18/
H A Dcx18-mailbox.c386 u32 ack_irq, req; in mb_ack_irq() local
390 ack_irq = IRQ_EPU_TO_APU_ACK; in mb_ack_irq()
394 ack_irq = IRQ_EPU_TO_CPU_ACK; in mb_ack_irq()
413 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); in mb_ack_irq()
/linux/arch/alpha/include/asm/
H A Dmachvec.h76 void (*ack_irq)(unsigned long); member