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/linux/include/linux/
H A Dcleanup.h197 #define DEFINE_FREE(_name, _type, _free) \ argument
198 static inline void __free_##_name(void *p) { _type _T = *(_type *)p; _free; }
200 #define __free(_name) __cleanup(__free_##_name) argument
243 #define DEFINE_CLASS(_name, _type, _exit, _init, _init_args...) \ argument
244 typedef _type class_##_name##_t; \
245 static inline void class_##_name##_destructor(_type *p) \
247 static inline _type class_##_name##_constructor(_init_args) \
250 #define EXTEND_CLASS(_name, ext, _init, _init_args...) \ argument
251 typedef class_##_name##_t class_##_name##ext##_t; \
252 static inline void class_##_name##ext##_destructor(class_##_name##_t *p)\
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H A Dhwmon-sysfs.h20 #define SENSOR_ATTR(_name, _mode, _show, _store, _index) \ argument
21 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
24 #define SENSOR_ATTR_RO(_name, _func, _index) \ argument
25 SENSOR_ATTR(_name, 0444, _func##_show, NULL, _index)
27 #define SENSOR_ATTR_RW(_name, _func, _index) \ argument
28 SENSOR_ATTR(_name, 0644, _func##_show, _func##_store, _index)
30 #define SENSOR_ATTR_WO(_name, _func, _index) \ argument
31 SENSOR_ATTR(_name, 0200, NULL, _func##_store, _index)
33 #define SENSOR_DEVICE_ATTR(_name, _mode, _show, _store, _index) \ argument
34 struct sensor_device_attribute sensor_dev_attr_##_name \
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H A Dconfigfs.h123 #define CONFIGFS_ATTR(_pfx, _name) \ argument
124 static struct configfs_attribute _pfx##attr_##_name = { \
125 .ca_name = __stringify(_name), \
128 .show = _pfx##_name##_show, \
129 .store = _pfx##_name##_store, \
132 #define CONFIGFS_ATTR_RO(_pfx, _name) \ argument
133 static struct configfs_attribute _pfx##attr_##_name = { \
134 .ca_name = __stringify(_name), \
137 .show = _pfx##_name##_show, \
140 #define CONFIGFS_ATTR_WO(_pfx, _name) \ argument
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/linux/include/linux/iio/
H A Dsysfs.h54 #define IIO_ATTR(_name, _mode, _show, _store, _addr) \ argument
55 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
58 #define IIO_ATTR_RO(_name, _addr) \ argument
59 { .dev_attr = __ATTR_RO(_name), \
62 #define IIO_ATTR_WO(_name, _addr) \ argument
63 { .dev_attr = __ATTR_WO(_name), \
66 #define IIO_ATTR_RW(_name, _addr) \ argument
67 { .dev_attr = __ATTR_RW(_name), \
70 #define IIO_DEVICE_ATTR(_name, _mode, _show, _store, _addr) \ argument
71 struct iio_dev_attr iio_dev_attr_##_name \
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/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_interface.h16 #define _reg_all(_name) ODM_##_name argument
17 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
18 #define _bit_all(_name) BIT_##_name argument
19 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
29 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
30 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
32 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
37 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
/linux/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
42 .hw.init = _fn(_name, _parent, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
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H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h141 #define DEF_TYPE(_name, _id, _type...) \ argument
142 { .name = _name, .id = _id, .type = _type }
143 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
144 DEF_TYPE(_name, _id, _type, .parent = _parent)
145 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
146 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
147 #define DEF_G3S_PLL(_name, _id, _parent, _conf) \ argument
148 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
149 #define DEF_INPUT(_name, _id) \ argument
150 DEF_TYPE(_name, _id, CLK_TYPE_IN)
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H A Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
43 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
48 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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H A Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
41 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
42 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
46 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
47 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
49 #define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \ argument
50 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx)
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H A Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \ argument
45 { .name = _name, .id = _id, .type = _type }
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
49 #define DEF_INPUT(_name, _id) \ argument
50 DEF_TYPE(_name, _id, CLK_TYPE_IN)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.h69 #define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags) \ argument
70 struct cv1800_clk_gate _name = { \
71 .common = CV1800_CLK_COMMON(#_name, _parent, \
77 #define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
81 .common = CV1800_CLK_COMMON(#_name, _parent, \
93 #define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
96 .common = CV1800_CLK_COMMON(#_name, _parent, \
105 #define CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
108 struct cv1800_clk_div _name = \
109 _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
96 .hw.init = CLK_HW_INIT(_name, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
119 .hw.init = CLK_HW_INIT_HW(_name, \
127 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
139 .hw.init = CLK_HW_INIT_PARENTS(_name, \
146 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \ argument
158 .hw.init = CLK_HW_INIT_PARENTS(_name, \
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H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
24 .hw.init = CLK_HW_INIT(_name, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
36 .hw.init = CLK_HW_INIT_HW(_name, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
48 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
64 .hw.init = CLK_HW_INIT_HWS(_name, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
79 .hw.init = CLK_HW_INIT_HWS(_name, \
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H A Dccu_mux.h49 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \ argument
57 .hw.init = CLK_HW_INIT_PARENTS(_name, \
65 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \ argument
68 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
73 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
76 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
82 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
88 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
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/linux/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
56 [prefix ## _name] = { \
63 .id = prefix ## _name, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
69 .vsel_shift = prefix ## _vsel_reg ## _ ## _name ## VSEL,\
70 .vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
74 [prefix ## _name] = { \
81 .id = prefix ## _name, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
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/linux/include/rdma/
H A Dib_sysfs.h21 #define IB_PORT_ATTR_RW(_name) \ argument
22 struct ib_port_attribute ib_port_attr_##_name = __ATTR_RW(_name)
24 #define IB_PORT_ATTR_ADMIN_RW(_name) \ argument
25 struct ib_port_attribute ib_port_attr_##_name = \
26 __ATTR_RW_MODE(_name, 0600)
28 #define IB_PORT_ATTR_RO(_name) \ argument
29 struct ib_port_attribute ib_port_attr_##_name = __ATTR_RO(_name)
31 #define IB_PORT_ATTR_WO(_name) \ argument
32 struct ib_port_attribute ib_port_attr_##_name = __ATTR_WO(_name)
/linux/drivers/clk/mediatek/
H A Dclk-mtk.h37 #define GATE_DUMMY(_id, _name) { \ argument
39 .name = _name, \
51 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
53 .name = _name, \
72 #define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ argument
74 .name = _name, \
81 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
82 FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
115 .name = _name, \
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H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
60 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
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/linux/include/trace/events/
H A Dmmflags.h132 #define IF_HAVE_PG_MLOCK(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
134 #define IF_HAVE_PG_MLOCK(_name) argument
138 #define IF_HAVE_PG_HWPOISON(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
140 #define IF_HAVE_PG_HWPOISON(_name) argument
144 #define IF_HAVE_PG_IDLE(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
146 #define IF_HAVE_PG_IDLE(_name) argument
150 #define IF_HAVE_PG_ARCH_2(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
152 #define IF_HAVE_PG_ARCH_2(_name) argument
156 #define IF_HAVE_PG_ARCH_3(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
158 #define IF_HAVE_PG_ARCH_3(_name) argument
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c129 #define PERIPH_GATE(_name, _bit) \ argument
130 struct clk_gate gate_##_name = { \
138 #define PERIPH_MUX(_name, _shift) \ argument
139 struct clk_mux mux_##_name = { \
148 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
149 struct clk_double_div rate_##_name = { \
159 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
160 struct clk_divider rate_##_name = { \
169 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ argument
170 struct clk_pm_cpu muxrate_##_name = { \
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/linux/fs/erofs/
H A Dsysfs.c29 #define EROFS_ATTR(_name, _mode, _id) \ argument
30 static struct erofs_attr erofs_attr_##_name = { \
31 .attr = {.name = __stringify(_name), .mode = _mode }, \
34 #define EROFS_ATTR_FUNC(_name, _mode) EROFS_ATTR(_name, _mode, _name) argument
35 #define EROFS_ATTR_FEATURE(_name) EROFS_ATTR(_name, 0444, feature) argument
37 #define EROFS_ATTR_OFFSET(_name, _mode, _id, _struct) \ argument
38 static struct erofs_attr erofs_attr_##_name = { \
39 .attr = {.name = __stringify(_name), .mode = _mode }, \
42 .offset = offsetof(struct _struct, _name),\
45 #define EROFS_ATTR_RW(_name, _id, _struct) \ argument
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/linux/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_pm.h101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
102 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
103 .attr_id = device_attr_id__##_name, \
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
108 __AMDGPU_DEVICE_ATTR(_name, _mode, \
109 amdgpu_get_##_name, amdgpu_set_##_name, \
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
113 AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
117 __AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
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/linux/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
24 .name = _name, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
44 .name = _name, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
65 .name = _name, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
75 .name = _name, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
90 .name = _name, \
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