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/linux/include/linux/
H A Dhwmon-sysfs.h20 #define SENSOR_ATTR(_name, _mode, _show, _store, _index) \ argument
21 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
24 #define SENSOR_ATTR_RO(_name, _func, _index) \ argument
25 SENSOR_ATTR(_name, 0444, _func##_show, NULL, _index)
27 #define SENSOR_ATTR_RW(_name, _func, _index) \ argument
28 SENSOR_ATTR(_name, 0644, _func##_show, _func##_store, _index)
30 #define SENSOR_ATTR_WO(_name, _func, _index) \ argument
31 SENSOR_ATTR(_name, 0200, NULL, _func##_store, _index)
33 #define SENSOR_DEVICE_ATTR(_name, _mode, _show, _store, _index) \ argument
34 struct sensor_device_attribute sensor_dev_attr_##_name \
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H A Dsysfs.h240 #define __ATTR(_name, _mode, _show, _store) { \ argument
241 .attr = {.name = __stringify(_name), \
247 #define __ATTR_PREALLOC(_name, _mode, _show, _store) { \ argument
248 .attr = {.name = __stringify(_name), \
254 #define __ATTR_RO_MODE(_name, _mode) { \ argument
255 .attr = { .name = __stringify(_name), \
257 .show = _name##_show, \
260 #define __ATTR_RO(_name) \ argument
261 __ATTR_RO_MODE(_name, 0444)
263 #define __ATTR_RW_MODE(_name, _mod argument
266 __ATTR_WO(_name) global() argument
269 __ATTR_RW(_name) global() argument
274 __ATTR_IGNORE_LOCKDEP(_name,_mode,_show,_store) global() argument
284 __ATTRIBUTE_GROUPS(_name) global() argument
290 ATTRIBUTE_GROUPS(_name) global() argument
301 BIN_ATTRIBUTE_GROUPS(_name) global() argument
339 __BIN_ATTR(_name,_mode,_read,_write,_size) global() argument
346 __BIN_ATTR_RO(_name,_size) global() argument
349 __BIN_ATTR_WO(_name,_size) global() argument
352 __BIN_ATTR_RW(_name,_size) global() argument
357 BIN_ATTR(_name,_mode,_read,_write,_size) global() argument
361 BIN_ATTR_RO(_name,_size) global() argument
364 BIN_ATTR_WO(_name,_size) global() argument
367 BIN_ATTR_RW(_name,_size) global() argument
371 __BIN_ATTR_ADMIN_RO(_name,_size) global() argument
374 __BIN_ATTR_ADMIN_RW(_name,_size) global() argument
377 BIN_ATTR_ADMIN_RO(_name,_size) global() argument
380 BIN_ATTR_ADMIN_RW(_name,_size) global() argument
383 __BIN_ATTR_SIMPLE_RO(_name,_mode) global() argument
386 BIN_ATTR_SIMPLE_RO(_name) global() argument
389 BIN_ATTR_SIMPLE_ADMIN_RO(_name) global() argument
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H A Dconfigfs.h123 #define CONFIGFS_ATTR_PERM(_pfx, _name, _perm) \ argument
124 static struct configfs_attribute _pfx##attr_##_name = { \
125 .ca_name = __stringify(_name), \
128 .show = _pfx##_name##_show, \
129 .store = _pfx##_name##_store, \
132 #define CONFIGFS_ATTR(_pfx, _name) CONFIGFS_ATTR_PERM( \ argument
133 _pfx, _name, S_IRUGO | S_IWUSR \
136 #define CONFIGFS_ATTR_RO(_pfx, _name) \ argument
137 static struct configfs_attribute _pfx##attr_##_name = { \
138 .ca_name = __stringify(_name), \
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/linux/include/linux/iio/
H A Dsysfs.h54 #define IIO_ATTR(_name, _mode, _show, _store, _addr) \ argument
55 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
58 #define IIO_ATTR_RO(_name, _addr) \ argument
59 { .dev_attr = __ATTR_RO(_name), \
62 #define IIO_ATTR_WO(_name, _addr) \ argument
63 { .dev_attr = __ATTR_WO(_name), \
66 #define IIO_ATTR_RW(_name, _addr) \ argument
67 { .dev_attr = __ATTR_RW(_name), \
70 #define IIO_DEVICE_ATTR(_name, _mode, _show, _store, _addr) \ argument
71 struct iio_dev_attr iio_dev_attr_##_name \
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/linux/drivers/thermal/qcom/
H A Dtsens.h90 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
91 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
92 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
93 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
94 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
95 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
96 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
97 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
98 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
99 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
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/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_interface.h16 #define _reg_all(_name) ODM_##_name argument
17 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
18 #define _bit_all(_name) BIT_##_name argument
19 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
29 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
30 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
32 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
37 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h149 #define DEF_TYPE(_name, _id, _type...) \ argument
150 { .name = _name, .id = _id, .type = _type }
151 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
152 DEF_TYPE(_name, _id, _type, .parent = _parent)
153 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
154 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
155 #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ argument
156 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
158 #define DEF_INPUT(_name, _id) \ argument
159 DEF_TYPE(_name, _id, CLK_TYPE_IN)
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H A Drzv2h-cpg.h208 #define DEF_TYPE(_name, _id, _type...) \ argument
209 { .name = _name, .id = _id, .type = _type }
210 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
211 DEF_TYPE(_name, _id, _type, .parent = _parent)
212 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ argument
213 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
214 #define DEF_INPUT(_name, _id) \ argument
215 DEF_TYPE(_name, _id, CLK_TYPE_IN)
216 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
217 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.h69 #define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags) \ argument
70 struct cv1800_clk_gate _name = { \
71 .common = CV1800_CLK_COMMON(#_name, _parent, \
77 #define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
81 .common = CV1800_CLK_COMMON(#_name, _parent, \
93 #define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
96 .common = CV1800_CLK_COMMON(#_name, _parent, \
105 #define CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \ argument
108 struct cv1800_clk_div _name = \
109 _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
96 .hw.init = CLK_HW_INIT(_name, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
119 .hw.init = CLK_HW_INIT_HW(_name, \
127 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
139 .hw.init = CLK_HW_INIT_PARENTS(_name, \
146 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \ argument
158 .hw.init = CLK_HW_INIT_PARENTS(_name, \
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H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
48 .hw.init = CLK_HW_INIT_PARENTS(_name, \
55 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, \ argument
70 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
77 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
89 .hw.init = CLK_HW_INIT_PARENTS(_name, \
96 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
101 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
107 #define SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(_struct, _name, _parents, _reg, \ argument
123 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
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H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
24 .hw.init = CLK_HW_INIT(_name, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
36 .hw.init = CLK_HW_INIT_HW(_name, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
48 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
64 .hw.init = CLK_HW_INIT_HWS(_name, \
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
79 .hw.init = CLK_HW_INIT_HWS(_name, \
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/linux/drivers/clk/meson/
H A Dmeson-clkc-utils.h30 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ argument
31 struct clk_regmap _name = { \
37 .name = #_name, \
45 #define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ argument
46 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
48 #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ argument
49 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
52 #define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ argument
54 struct clk_regmap _prefix##_name##_sel = { \
63 .name = #_name "_sel", \
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/linux/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
56 [prefix ## _name] = { \
63 .id = prefix ## _name, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
69 .vsel_shift = prefix ## _vsel_reg ## _ ## _name ## VSEL,\
70 .vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
74 [prefix ## _name] = { \
81 .id = prefix ## _name, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
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/linux/include/rdma/
H A Dib_sysfs.h21 #define IB_PORT_ATTR_RW(_name) \ argument
22 struct ib_port_attribute ib_port_attr_##_name = __ATTR_RW(_name)
24 #define IB_PORT_ATTR_ADMIN_RW(_name) \ argument
25 struct ib_port_attribute ib_port_attr_##_name = \
26 __ATTR_RW_MODE(_name, 0600)
28 #define IB_PORT_ATTR_RO(_name) \ argument
29 struct ib_port_attribute ib_port_attr_##_name = __ATTR_RO(_name)
31 #define IB_PORT_ATTR_WO(_name) \ argument
32 struct ib_port_attribute ib_port_attr_##_name = __ATTR_WO(_name)
/linux/tools/perf/tests/
H A Dtests.h52 #define TEST_CASE(description, _name) \ argument
54 .name = #_name, \
56 .run_case = test__##_name, \
59 #define TEST_CASE_REASON(description, _name, _reason) \ argument
61 .name = #_name, \
63 .run_case = test__##_name, \
67 #define TEST_CASE_EXCLUSIVE(description, _name) \ argument
69 .name = #_name, \
71 .run_case = test__##_name, \
75 #define TEST_CASE_REASON_EXCLUSIVE(description, _name, _reason) \ argument
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/linux/drivers/clk/mediatek/
H A Dclk-mtk.h39 #define GATE_DUMMY(_id, _name) { \ argument
41 .name = _name, \
53 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
55 .name = _name, \
74 #define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ argument
76 .name = _name, \
83 #define FACTOR(_id, _name, _parent, _mult, _div) \ argument
84 FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
114 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
117 .name = _name, \
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H A Dclk-mt8188-infra_ao.c45 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
49 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
56 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
59 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
60 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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H A Dclk-mux.h47 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
52 .name = _name, \
68 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
71 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
76 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ argument
79 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
89 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
92 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
97 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ argument
100 GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
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H A Dclk-mt8196-venc.c42 #define GATE_VEN10(_id, _name, _parent, _shift) { \ argument
44 .name = _name, \
52 #define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
54 .name = _name, \
64 #define GATE_HWV_VEN10(_id, _name, _parent, _shift) \ argument
65 GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
67 #define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \ argument
69 .name = _name, \
114 #define GATE_VEN20(_id, _name, _parent, _shift) { \ argument
116 .name = _name, \
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H A Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
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/linux/include/trace/events/
H A Dmmflags.h111 #define IF_HAVE_PG_MLOCK(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
113 #define IF_HAVE_PG_MLOCK(_name) argument
117 #define IF_HAVE_PG_HWPOISON(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
119 #define IF_HAVE_PG_HWPOISON(_name) argument
123 #define IF_HAVE_PG_IDLE(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
125 #define IF_HAVE_PG_IDLE(_name) argument
129 #define IF_HAVE_PG_ARCH_2(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
131 #define IF_HAVE_PG_ARCH_2(_name) argument
135 #define IF_HAVE_PG_ARCH_3(_name) ,{1UL << PG_##_name, __stringify(_name)} argument
137 #define IF_HAVE_PG_ARCH_3(_name) argument
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/linux/drivers/clk/sprd/
H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
56 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c129 #define PERIPH_GATE(_name, _bit) \ argument
130 struct clk_gate gate_##_name = { \
138 #define PERIPH_MUX(_name, _shift) \ argument
139 struct clk_mux mux_##_name = { \
148 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
149 struct clk_double_div rate_##_name = { \
159 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
160 struct clk_divider rate_##_name = { \
169 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ argument
170 struct clk_pm_cpu muxrate_##_name = { \
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/linux/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_pm.h101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
102 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
103 .attr_id = device_attr_id__##_name, \
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
108 __AMDGPU_DEVICE_ATTR(_name, _mode, \
109 amdgpu_get_##_name, amdgpu_set_##_name, \
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
113 AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
117 __AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
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