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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
47 .flags = _flags, \
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
58 .flags = _flags, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
89 _table, _gate, _flags) \ argument
99 _flags), \
[all …]
H A Dccu_mp.h38 _gate, _postdiv, _flags) \ argument
51 _flags), \
60 _gate, _postdiv, _flags)\ argument
73 _flags), \
81 _gate, _flags) \ argument
92 _flags), \
100 _flags) \ argument
105 0, _flags)
112 _flags) \ argument
126 _flags), \
[all …]
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
27 _flags), \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
39 _flags), \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
51 _flags), \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
67 _flags), \
72 _gate, _prediv, _flags) \ argument
82 _flags), \
[all …]
H A Dccu_mux.h51 _flags, _features) \ argument
60 _flags), \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
75 _flags) \ argument
78 _width, _gate, _flags, 0)
81 _shift, _width, _gate, _flags) \ argument
84 _flags)
87 _flags) \ argument
89 _reg, _shift, _width, 0, _flags)
[all …]
H A Dccu_nm.h43 _gate, _lock, _flags) \ argument
57 _flags), \
66 _gate, _lock, _flags) \ argument
81 _flags), \
91 _gate, _lock, _flags) \ argument
107 _flags), \
119 _gate, _lock, _flags, \ argument
137 _flags), \
149 _gate, _lock, _flags) \ argument
158 _gate, _lock, _flags, \
[all …]
H A Dccu_nkm.h41 _gate, _lock, _flags) \ argument
54 _flags), \
62 _gate, _lock, _flags) \ argument
74 _flags), \
/linux/drivers/clk/spacemit/
H A Dccu_mix.h55 #define CCU_MIX_INITHW(_name, _parent, _ops, _flags) \ argument
57 .flags = _flags, \
65 #define CCU_MIX_INITHW_PARENTS(_name, _parents, _ops, _flags) \ argument
66 .hw.init = CLK_HW_INIT_PARENTS_DATA(#_name, _parents, &_ops, _flags)
68 #define CCU_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _flags) \ argument
73 CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \
85 #define CCU_MUX_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, _flags) \ argument
91 _flags), \
95 #define CCU_DIV_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, _flags) \ argument
100 CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_ops, _flags) \
[all …]
H A Dccu_ddn.h24 #define CCU_DDN_INIT(_name, _parent, _flags) \ argument
25 CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
28 _den_shift, _den_width, _pre_div, _flags) \ argument
32 .hw.init = CCU_DDN_INIT(_name, _parent, _flags), \
H A Dccu_pll.h57 #define CCU_PLL_HWINIT(_name, _flags) \ argument
63 .flags = _flags, \
67 _mask_lock, _flags) \ argument
73 .hw.init = CCU_PLL_HWINIT(_name, _flags) \
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.h69 #define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags) \ argument
73 _flags), \
79 _div_flag, _ops, _flags) \ argument
82 _ops, _flags), \
94 _fix_div, _ops, _flags) \ argument
97 _ops, _flags), \
107 _div_flag, _flags) \ argument
111 _div_flag, &cv1800_clk_div_ops, _flags)
115 _div_flag, _bypass_reg, _bypass_shift, _flags)\ argument
122 _flags), \
[all …]
/linux/drivers/clk/sprd/
H A Dcomposite.h23 _dwidth, _flags, _fn) \ argument
31 &sprd_comp_ops, _flags), \
36 _mshift, _mwidth, _dshift, _dwidth, _flags) \ argument
39 _dwidth, _flags, CLK_HW_INIT_PARENTS)
42 _mwidth, _dshift, _dwidth, _flags) \ argument
44 _mshift, _mwidth, _dshift, _dwidth, _flags)
48 _dwidth, _flags) \ argument
51 _dwidth, _flags, \
55 _mwidth, _dshift, _dwidth, _flags) \ argument
58 _flags)
[all …]
H A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
47 &sprd_mux_ops, _flags), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
71 _reg, _shift, _width, _flags)
H A Ddiv.h41 _shift, _width, _flags, _fn) \ argument
48 &sprd_div_ops, _flags), \
53 _shift, _width, _flags) \ argument
55 _shift, _width, _flags, CLK_HW_INIT)
58 _shift, _width, _flags) \ argument
60 _shift, _width, _flags, CLK_HW_INIT_FW_NAME)
63 _shift, _width, _flags) \ argument
65 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux/drivers/clk/actions/
H A Dowl-composite.h38 _mux, _gate, _div, _flags) \ argument
48 _flags), \
53 _gate, _div, _flags) \ argument
62 _flags), \
67 _mux, _gate, _factor, _flags) \ argument
77 _flags), \
82 _gate, _mul, _div, _flags) \ argument
93 _flags), \
98 _mux, _gate, _flags) \ argument
107 _flags), \
H A Dowl-pll.h56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
66 _flags), \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
80 _flags), \
86 _flags) \ argument
95 _flags), \
H A Dowl-gate.h35 _bit_idx, _gate_flags, _flags) \ argument
43 _flags), \
48 _bit_idx, _gate_flags, _flags) \ argument
55 _flags), \
/linux/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_pm.h101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
104 .flags = _flags, \
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
110 _flags, ##__VA_ARGS__)
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
114 _flags, ##__VA_ARGS__)
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
119 _flags, ##__VA_ARGS__)
/linux/drivers/net/ethernet/fungible/funcore/
H A Dfun_hci.h39 #define FUN_ADMIN_REQ_COMMON_INIT(_op, _len8, _flags, _suboff8, _cid) \ argument
41 .op = (_op), .len8 = (_len8), .flags = cpu_to_be16(_flags), \
157 #define FUN_ADMIN_SIMPLE_SUBOP_INIT(_subop, _flags, _data) \ argument
159 .subop = (_subop), .flags = cpu_to_be16(_flags), \
254 _subop, _flags, _id, _epsqid, _entry_size_log2, _nentries, _address, \ argument
259 .subop = (_subop), .flags = cpu_to_be16(_flags), \
274 #define FUN_ADMIN_EPCQ_MODIFY_REQ_INIT(_subop, _flags, _id, _headroom) \ argument
276 .subop = (_subop), .flags = cpu_to_be16(_flags), \
329 _subop, _flags, _id, _epcqid, _entry_size_log2, _nentries, _address, \ argument
334 .subop = (_subop), .flags = cpu_to_be16(_flags), \
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mux.h50 _upd, _flags, _ops) { \ argument
64 .flags = _flags, \
70 _gate, _upd_ofs, _upd, _flags, _ops) \ argument
74 _gate, _upd_ofs, _upd, _flags, _ops) \
78 _width, _gate, _upd_ofs, _upd, _flags, _ops) \ argument
82 _gate, _upd_ofs, _upd, _flags, _ops) \
91 _gate, _upd_ofs, _upd, _flags) \ argument
94 _gate, _upd_ofs, _upd, _flags, \
99 _shift, _width, _gate, _upd_ofs, _upd, _flags) \ argument
102 _shift, _width, _gate, _upd_ofs, _upd, _flags, \
[all …]
H A Dclk-mt7988-infracfg.c128 #define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
130 _flags)
132 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
134 _flags)
136 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
138 _flags)
140 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
142 _flags)
/linux/include/linux/gpio/
H A Dmachine.h69 #define GPIO_LOOKUP_SINGLE(_name, _dev_id, _key, _chip_hwnum, _con_id, _flags) \ argument
73 GPIO_LOOKUP(_key, _chip_hwnum, _con_id, _flags), \
81 #define GPIO_LOOKUP(_key, _chip_hwnum, _con_id, _flags) \ argument
82 GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, 0, _flags)
89 #define GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, _idx, _flags) \ argument
95 .flags = _flags, \
/linux/include/linux/
H A Dslab.h968 #define kmem_buckets_alloc(_b, _size, _flags) \ argument
969 alloc_hooks(__kmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE))
971 #define kmem_buckets_alloc_track_caller(_b, _size, _flags) \ argument
972 …alloc_hooks(__kmalloc_node_track_caller_noprof(PASS_BUCKET_PARAMS(_size, _b), _flags, NUMA_NO_NODE…
1079 #define kcalloc_node(_n, _size, _flags, _node) \ argument
1080 kmalloc_array_node(_n, _size, (_flags) | __GFP_ZERO, _node)
1085 #define kmem_cache_zalloc(_k, _flags) kmem_cache_alloc(_k, (_flags)|__GFP_ZERO) argument
1097 #define kzalloc_node(_size, _flags, _node) kmalloc_node(_size, (_flags)|__GFP_ZERO, _node) argument
1101 #define kvmalloc_node_align_noprof(_size, _align, _flags, _node) \ argument
1102 __kvmalloc_node_noprof(PASS_BUCKET_PARAMS(_size, NULL), _align, _flags, _node)
[all …]
H A Dsh_clk.h117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
123 .flags = _flags, \
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
158 .flags = _flags, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
180 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
194 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
/linux/drivers/clk/meson/
H A Dmeson-clkc-utils.h30 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ argument
41 .flags = (_flags), \
45 #define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ argument
46 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
48 #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ argument
49 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
/linux/lib/
H A Dtest_dynamic_debug.c42 #define DD_SYS_WRAP(_model, _flags) \ argument
44 static struct ddebug_class_param _flags##_model = { \
46 .flags = #_flags, \
49 module_param_cb(_flags##_##_model, &param_ops_dyndbg_classes, &_flags##_model, 0600)

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