| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-ip.h | 78 _div_reg, _div_shift, _div_width, _div_init, \ argument
85 .div = CV1800_CLK_REG(_div_reg, _div_shift, \
106 _div_reg, _div_shift, _div_width, _div_init, \ argument
110 _div_reg, _div_shift, _div_width, _div_init,\
114 _div_reg, _div_shift, _div_width, _div_init, \ argument
119 _div_reg, _div_shift, \
147 _div_reg, _div_shift, _div_width, _div_init, \ argument
156 .div = CV1800_CLK_REG(_div_reg, _div_shift, \
164 _div_reg, _div_shift, _div_width, _div_init, \ argument
169 _div_reg, _div_shift, _div_width, _div_init,\
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| /linux/drivers/clk/tegra/ |
| H A D | clk.h | 643 _div_shift, _div_width, _div_frac_width, \ argument
656 .shift = _div_shift, \
686 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ argument
696 _mux_flags, _div_shift, \
707 _mux_shift, _mux_width, _mux_flags, _div_shift, \ argument
712 _div_shift, _div_width, _div_frac_width, _div_flags, \
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| H A D | clk-tegra-periph.c | 838 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \ argument
843 .div_shift = _div_shift,\
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 163 _div_width, _div_shift) { \ argument
168 .divider_shift = _div_shift, \
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp1.c | 1323 #define _STM32_DIV(_div_offset, _div_shift, _div_width,\ argument
1328 .shift = _div_shift,\
1336 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\ argument
1337 _STM32_DIV(_div_offset, _div_shift, _div_width,\
1340 #define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\ argument
1341 _STM32_DIV(_div_offset, _div_shift, _div_width,\
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| /linux/drivers/clk/ |
| H A D | clk-bm1880.c | 144 _div_shift, _div_width, _div_initval, _table, \ argument
152 .div_shift = _div_shift, \
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| /linux/drivers/clk/meson/ |
| H A D | axg-audio.c | 85 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument
90 .shift = (_div_shift), \
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