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Searched refs:_clk (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/stm32/
H A Dclk-stm32-core.h163 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
167 .clock_cfg = (_struct) {_clk},\
171 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
172 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
175 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
176 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
179 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
180 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
183 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
184 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
/linux/include/linux/
H A Dsh_clk.h200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
/linux/arch/arm/mach-omap2/
H A Domap_hwmod.c635 } else if (oh->_clk) { in _get_clkdm()
636 if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk))) in _get_clkdm()
638 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); in _get_clkdm()
832 oh->_clk = clk; in _init_main_clk()
838 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk()
841 if (IS_ERR(oh->_clk)) { in _init_main_clk()
854 clk_prepare(oh->_clk); in _init_main_clk()
887 os->_clk = c; in _init_interface_clks()
896 clk_prepare(os->_clk); in _init_interface_clks()
924 oc->_clk = c; in _init_opt_clks()
[all …]
H A Domap_hwmod.h181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
H A Ddisplay.c383 clk_prepare_enable(oc->_clk); in omap_dss_reset()
409 clk_disable_unprepare(oc->_clk); in omap_dss_reset()
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
/linux/drivers/ufs/host/
H A Dufs-exynos.c529 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
534 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
535 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
536 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
538 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()