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Searched refs:__raw_writeq (Results 1 – 25 of 44) sorted by relevance

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/linux/arch/mips/sibyte/common/
H A Dsb_tbprof.c152 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
161 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | in arm_tb()
165 __raw_writeq( in arm_tb()
171 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | in arm_tb()
178 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
180 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in arm_tb()
185 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); in arm_tb()
199 __raw_writeq(M_SCD_TRACE_CFG_START_READ, in sbprof_tb_intr()
221 __raw_writeq(M_SCD_TRACE_CFG_RESET, in sbprof_tb_intr()
232 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in sbprof_tb_intr()
[all …]
/linux/arch/mips/kernel/
H A Dcevt-sb1250.c36 __raw_writeq(0, cfg); in sibyte_shutdown()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
51 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
64 __raw_writeq(0, cfg); in sibyte_next_event()
65 __raw_writeq(delta - 1, init); in sibyte_next_event()
66 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
129 __raw_writeq(IMR_IP4_VAL, in sb1250_clockevent_init()
H A Dcevt-bcm1480.c39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
53 __raw_writeq(0, cfg); in sibyte_shutdown()
65 __raw_writeq(0, cfg); in sibyte_next_event()
66 __raw_writeq(delta - 1, init); in sibyte_next_event()
67 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
129 __raw_writeq(IMR_IP4_VAL, in sb1480_clockevent_init()
H A Dcsrc-sb1250.c58 __raw_writeq(0, in sb1250_clocksource_init()
61 __raw_writeq(SB1250_HPT_VALUE, in sb1250_clocksource_init()
64 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, in sb1250_clocksource_init()
/linux/arch/mips/sibyte/swarm/
H A Drtc_m41t81.c88 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_read()
89 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, in m41t81_read()
95 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_read()
103 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_read()
115 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_write()
116 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); in m41t81_write()
117 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in m41t81_write()
125 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_write()
130 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_write()
H A Drtc_xicor1241.c63 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); in xicor_read()
64 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); in xicor_read()
65 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in xicor_read()
71 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in xicor_read()
79 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_read()
91 __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); in xicor_write()
92 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); in xicor_write()
93 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, in xicor_write()
101 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_write()
/linux/arch/mips/sibyte/sb1250/
H A Dirq.c155 __raw_writeq(pending, in ack_sb1250_irq()
230 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
234 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
247 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
250 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
255 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
257 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
262 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
263 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
/linux/arch/mips/sibyte/bcm1480/
H A Dirq.c168 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), in ack_bcm1480_irq()
172 …__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1… in ack_bcm1480_irq()
248 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
257 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
271 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + in arch_init_irq()
278 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
280 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
288 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); in arch_init_irq()
292 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); in arch_init_irq()
H A Dsmp.c69 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); in bcm1480_send_ipi_single()
169 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); in bcm1480_mailbox_interrupt()
/linux/include/asm-generic/
H A Dlogic_io.h63 #define __raw_writeq __raw_writeq macro
64 void __raw_writeq(u64 value, volatile void __iomem *addr);
/linux/arch/arm64/include/asm/
H A Dio.h46 #define __raw_writeq __raw_writeq macro
47 static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
238 __raw_writeq(*from, to); in __const_memcpy_toio_aligned64()
286 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
/linux/arch/riscv/include/asm/
H A Dmmio.h38 #define __raw_writeq __raw_writeq macro
39 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
98 #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_doorbell.h56 __raw_writeq((__force u64) val, dest); in mthca_write64_raw()
62 __raw_writeq((__force u64) cpu_to_be64((u64) hi << 32 | lo), dest); in mthca_write64()
/linux/drivers/i2c/busses/
H A Di2c-octeon-core.h140 __raw_writeq(val, addr); in octeon_i2c_writeq_flush()
157 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_write()
185 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_read()
/linux/arch/alpha/kernel/
H A Dio.c158 void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
170 EXPORT_SYMBOL(__raw_writeq);
229 __raw_writeq(b, addr); in writeq()
547 __raw_writeq(*(const u64 *)from, to); in memcpy_toio()
620 __raw_writeq(c, to); in _memset_c_io()
/linux/arch/sparc/include/asm/
H A Dio_64.h93 #define __raw_writeq __raw_writeq macro
94 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) in __raw_writeq() function
341 __raw_writeq(q, addr); in sbus_writeq()
/linux/arch/alpha/include/asm/
H A Dio.h269 extern void __raw_writeq(u64 b, volatile void __iomem *addr);
277 #define __raw_writeq __raw_writeq macro
498 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
530 __raw_writeq(b, addr); in writeq()
/linux/include/linux/mlx5/
H A Ddoorbell.h53 __raw_writeq(*(u64 *)val, dest); in mlx5_write64()
/linux/drivers/infiniband/hw/qib/
H A Dqib_pio_copy.c53 __raw_writeq(*src++, dst++); in qib_pio_copy()
/linux/include/linux/mlx4/
H A Ddoorbell.h58 __raw_writeq(*(u64 *) val, dest); in mlx4_write64()
/linux/lib/
H A Diomap_copy.c72 __raw_writeq(*src++, dst++); in __iowrite64_copy()
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_hw.h190 __raw_writeq(value, (void __iomem *)(epa.addr + offset)); in epa_store()
196 __raw_writeq(value, (void __iomem *)(epa.addr + offset)); in epa_store_acc()
/linux/drivers/net/ethernet/sfc/siena/
H A Dio.h87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
141 __raw_writeq((__force u64)value->u64[0], membase + addr); in efx_sram_writeq()
/linux/drivers/net/ethernet/sfc/falcon/
H A Dio.h70 __raw_writeq((__force u64)value, efx->membase + reg); in _ef4_writeq()
124 __raw_writeq((__force u64)value->u64[0], membase + addr); in ef4_sram_writeq()
/linux/arch/mips/include/asm/
H A Dmips-gic.h128 __raw_writeq(BIT(intr % 64), addr); \
147 __raw_writeq(_val, addr); \

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