| /linux/arch/x86/include/asm/ |
| H A D | div64.h | 24 unsigned long __upper, __low, __high, __mod, __base; \
25 __base = (base); \
26 if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \
27 __mod = n & (__base - 1); \
28 n >>= ilog2(__base); \
33 __upper = __high % (__base); \
34 __high = __high / (__base); \
37 : "rm" (__base), "0" (__low), "1" (__upper)); \
|
| /linux/drivers/iio/adc/ |
| H A D | nxp-sar-adc.c | 40 #define NXP_SAR_ADC_CDR(__base, __channel) (((__base) + 0x100) + ((__channel) * 0x4)) argument
46 #define NXP_SAR_ADC_MCR(__base) ((__base) + 0x00) argument
60 #define NXP_SAR_ADC_MSR(__base) ((__base) + 0x04) argument
66 #define NXP_SAR_ADC_ISR(__base) ((__base) + 0x10) argument
71 #define NXP_SAR_ADC_CEOCFR0(__base) ((__base) + 0x14) argument
72 #define NXP_SAR_ADC_CEOCFR1(__base) ((__base) + 0x18) argument
77 #define NXP_SAR_ADC_IMR(__base) ((__base) + 0x20) argument
80 #define NXP_SAR_ADC_CIMR0(__base) ((__base) + 0x24) argument
81 #define NXP_SAR_ADC_CIMR1(__base) ((__base) + 0x28) argument
84 #define NXP_SAR_ADC_DMAE(__base) ((__base) + 0x40) argument
[all …]
|
| /linux/drivers/watchdog/ |
| H A D | s32g_wdt.c | 20 #define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */ argument
26 #define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */ argument
28 #define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */ argument
32 #define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */ argument
|
| /linux/drivers/clocksource/ |
| H A D | timer-nxp-pit.c | 21 #define PITMCR(__base) (__base) argument
26 #define PITLDVAL(__base) (__base) argument
27 #define PITTCTRL(__base) ((__base) + 0x08) argument
30 #define PITCVAL(__base) ((__base) + 0x04) argument
35 #define PITTFLG(__base) ((__base) + 0x0c) argument
|
| /linux/arch/powerpc/boot/ |
| H A D | stdio.c | 33 unsigned int __base = (base); \
35 __rem = ((unsigned long long)(n)) % __base; \
36 (n) = ((unsigned long long)(n)) / __base; \
49 unsigned int __base = (base); \
53 __rem = (unsigned int)(n) % __base; \
54 (n) = (unsigned int)(n) / __base; \
56 __rem = __div64_32(&(n), __base); \
|
| /linux/arch/m68k/include/asm/ |
| H A D | div64.h | 19 unsigned long __base = (base); \
25 : "d" (__base), "0" (__n.n32[0])); \
29 : "d" (__base), "1" (__upper), "0" (__n.n32[1])); \
|
| /linux/arch/alpha/boot/ |
| H A D | stdio.c | 18 unsigned int __base = (base); \
20 __rem = ((unsigned long long)(n)) % __base; \
21 (n) = ((unsigned long long)(n)) / __base; \
|
| /linux/drivers/gpu/drm/vmwgfx/ |
| H A D | ttm_object.h | 285 #define ttm_base_object_kfree(__object, __base)\ argument
286 kfree_rcu(__object, __base.rhead)
|
| /linux/tools/sched_ext/include/scx/ |
| H A D | common.bpf.h | 247 u64 __base = (u64)&(base); \
248 u64 __addr = (u64)&((base) member) - __base; \
257 : "r"(__base), \
280 u64 __base = (u64)arr; \
281 u64 __addr = (u64)&(arr[i]) - __base; \
288 : "r"(__base), \
|
| /linux/drivers/net/ethernet/amd/ |
| H A D | sunlance.c | 277 do { void __iomem *__base = (__lp)->lregs; \
278 sbus_writew(LE_CSR0, __base + RAP); \
279 sbus_writew(LE_C0_STOP, __base + RDP); \
|
| /linux/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2x00queue.c | 1113 #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ in rt2x00queue_alloc_entries() argument
1114 (((char *)(__base)) + ((__limit) * (__esize)) + \ in rt2x00queue_alloc_entries()
|