Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL5 (Results 1 – 1 of 1) sorted by relevance
243 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 macro575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_pex_enable()578 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); in uphy_pex_enable()798 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_sata_enable()801 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); in uphy_sata_enable()