Searched refs:XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (Results 1 – 2 of 2) sorted by relevance
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) macro562 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; in pcie_phy_power_on()
56 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) macro1092 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; in tegra124_pcie_phy_power_on()