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Searched refs:XE_RTP_ACTIONS (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_wa.c106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
[all …]
H A Dxe_tuning.c21 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
25 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
37 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
42 XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
47 XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
52 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
56 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
60 XE_RTP_ACTIONS(SET(L3SQCREG2,
65 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
[all …]
H A Dxe_reg_whitelist.c31 XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
37 XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
41 XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
45 XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
51 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
60 XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
67 XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
72 XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
83 XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
H A Dxe_hw_engine.c383 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), in xe_hw_engine_setup_default_lrc_state()
392 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, in xe_hw_engine_setup_default_lrc_state()
398 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0), in xe_hw_engine_setup_default_lrc_state()
434 XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), in hw_engine_setup_default_state()
448 XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0), in hw_engine_setup_default_state()
459 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, in hw_engine_setup_default_state()
H A Dxe_rtp.h417 #define XE_RTP_ACTIONS(...) \ macro
/linux/drivers/gpu/drm/xe/tests/
H A Dxe_rtp_test.c73 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
77 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
93 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
97 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
112 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
118 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
122 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(2)))
126 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(3)))
138 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
147 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
[all …]