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Searched refs:XE_RTP_ACTIONS (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_wa.c140 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
145 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
149 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
154 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
159 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
165 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
170 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL, DIS_PEND_GPA_LINK))
177 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
181 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
188 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
[all …]
H A Dxe_tuning.c26 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
30 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
37 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
42 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
48 XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
53 XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
58 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
62 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
67 XE_RTP_ACTIONS(SET(L3SQCREG2,
73 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
[all …]
H A Dxe_reg_whitelist.c49 XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
55 XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
59 XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
63 XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
69 XE_RTP_ACTIONS(WHITELIST(RING_QUEUE_TIMESTAMP(0),
75 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
84 XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
91 XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
95 XE_RTP_ACTIONS(WHITELIST(FF_MODE,
103 XE_RTP_ACTIONS(WHITELIST(FF_MODE,
[all …]
H A Dxe_hw_engine.c355 XE_RTP_ACTIONS(FIELD_SET_FUNC(BLIT_CCTL(0),
364 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
416 XE_RTP_ACTIONS(FIELD_SET_FUNC(RING_CMD_CCTL(0),
424 XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
429 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
440 XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
451 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
457 XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
462 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
467 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
H A Dxe_rtp.h477 #define XE_RTP_ACTIONS(...) \ macro
/linux/drivers/gpu/drm/xe/tests/
H A Dxe_rtp_test.c300 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
304 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
319 XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
325 XE_RTP_ACTIONS(FIELD_SET_FUNC(REGULAR_REG1,
342 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
346 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
361 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
365 XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))
380 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
384 XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))
[all …]