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Searched refs:WatermarkRow (Results 1 – 25 of 39) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c726 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
730 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
734 table->WatermarkRow[1][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
738 table->WatermarkRow[1][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
742 table->WatermarkRow[1][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
747 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
751 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
755 table->WatermarkRow[0][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
759 table->WatermarkRow[0][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
763 table->WatermarkRow[0][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c875 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn35_build_watermark_ranges()
876 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn35_build_watermark_ranges()
878 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
879 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
881 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn35_build_watermark_ranges()
883 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn35_build_watermark_ranges()
886 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn35_build_watermark_ranges()
889 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn35_build_watermark_ranges()
894 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
895 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
[all …]
H A Ddcn35_smu.h71 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
169 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c428 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
430 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
432 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
434 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
437 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
442 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
444 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
446 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
448 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
451 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c684 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
686 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
688 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
690 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
693 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
698 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
700 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
702 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
704 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
707 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c519 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
521 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
523 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
525 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
528 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
533 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
535 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
537 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
539 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
542 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
345 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
346 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; in dcn3_notify_wm_ranges()
347 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
H A Ddcn30_smu11_driver_if.h53 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1068 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1070 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1072 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table()
1074 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table()
1077 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table()
1079 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
1084 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
1086 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
1088 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table()
1090 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in renoir_set_watermarks_table()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c588 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v15_0_0_set_watermarks_table()
590 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v15_0_0_set_watermarks_table()
592 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v15_0_0_set_watermarks_table()
594 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v15_0_0_set_watermarks_table()
597 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v15_0_0_set_watermarks_table()
602 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v15_0_0_set_watermarks_table()
604 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v15_0_0_set_watermarks_table()
606 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v15_0_0_set_watermarks_table()
608 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v15_0_0_set_watermarks_table()
611 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v15_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c501 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table()
503 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v14_0_0_set_watermarks_table()
505 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v14_0_0_set_watermarks_table()
507 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v14_0_0_set_watermarks_table()
510 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v14_0_0_set_watermarks_table()
515 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table()
517 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v14_0_0_set_watermarks_table()
519 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v14_0_0_set_watermarks_table()
521 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v14_0_0_set_watermarks_table()
524 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v14_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_smu14_driver_if.h43 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_smu13_driver_if.h42 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
H A Dsmu13_driver_if_yellow_carp.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
H A Dsmu12_driver_if.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
H A Dsmu13_driver_if_v13_0_4.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
H A Dsmu11_driver_if_vangogh.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h90 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c1613 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table()
1615 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1617 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table()
1619 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1622 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in vangogh_set_watermarks_table()
1627 table->WatermarkRow[WM_SOCCLK][i].MinClock = in vangogh_set_watermarks_table()
1629 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table()
1631 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in vangogh_set_watermarks_table()
1633 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1636 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in vangogh_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h98 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member

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