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Searched refs:WRITE_REG (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c132 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
134 do { WRITE_REG(priv, regIMR, 0); } while (0)
174 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); in bdx_fifo_init()
175 WRITE_REG(priv, reg_CFG1, H32_64(f->da)); in bdx_fifo_init()
346 WRITE_REG(priv, regINIT_SEMAPHORE, 1); in bdx_fw_load()
374 WRITE_REG(priv, regUNC_MAC2_A, val); in bdx_restore_mac()
376 WRITE_REG(priv, regUNC_MAC1_A, val); in bdx_restore_mac()
378 WRITE_REG(priv, regUNC_MAC0_A, val); in bdx_restore_mac()
399 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); in bdx_hw_start()
400 WRITE_REG(priv, regPAUSE_QUANT, 0x96); in bdx_hw_start()
[all …]
H A Dtehuti.h98 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) macro
/linux/drivers/ata/
H A Dpata_optidma.c39 WRITE_REG = 1, /* index of Write cycle timing register */ enumerator
170 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); in optidma_mode_setup()
173 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); in optidma_mode_setup()
/linux/drivers/gpu/drm/amd/include/
H A Dmes_v11_api_def.h631 struct WRITE_REG { struct
712 struct WRITE_REG write_reg;
/linux/drivers/parisc/
H A Dlba_pci.c932 WRITE_REG##size(val, astro_iop_base + addr); \
990 WRITE_REG##size(val, where); \