Searched refs:WREG32_XCC (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gc_9_4_3.c | 303 WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst); in kgd_gfx_v9_4_3_hqd_load()
493 WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
498 WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
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| H A D | gmc_v9_0.c | 506 WREG32_XCC(reg, tmp, j); in gmc_v9_0_vm_fault_interrupt_state()
534 WREG32_XCC(reg, tmp, j); in gmc_v9_0_vm_fault_interrupt_state()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 242 WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst); in kgd_gfx_v9_hqd_load()
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| H A D | gfx_v9_4_3.c | 3129 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3135 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3194 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); in gfx_v9_4_3_set_priv_reg_fault_state()
3234 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); in gfx_v9_4_3_set_bad_op_fault_state()
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| H A D | amdgpu.h | 1315 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) macro
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