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Searched refs:WREG32_SOC15_RLC (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c309 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
344 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
351 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, in kgd_gfx_v9_4_3_hqd_load()
355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
H A Dmmhub_v2_0.c210 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
215 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
217 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
228 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
229 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
230 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
337 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); in mmhub_v2_0_enable_system_domain()
H A Damdgpu_amdkfd_gfx_v9.c94 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load()
277 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_hqd_load()
279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load()
281 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_hqd_load()
283 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_hqd_load()
285 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_hqd_load()
290 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR, in kgd_gfx_v9_hqd_load()
294 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data); in kgd_gfx_v9_hqd_load()
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H A Dsoc15_common.h172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ macro