Home
last modified time | relevance | path

Searched refs:WREG32_OR (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dr600_hdmi.c232 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_avi_packet()
235 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_avi_packet()
346 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, in r600_set_vbi_packet()
367 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_set_audio_packet()
400 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in r600_set_mute()
454 WREG32_OR(HDMI0_CONTROL + offset, in r600_hdmi_update_audio_settings()
462 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in r600_hdmi_update_audio_settings()
488 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); in r600_hdmi_enable()
496 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); in r600_hdmi_enable()
504 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); in r600_hdmi_enable()
H A Ddce3_1_afmt.c216 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, in dce3_2_set_audio_packet()
220 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, in dce3_2_set_audio_packet()
230 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); in dce3_2_set_mute()
H A Devergreen_hdmi.c386 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, in dce4_set_audio_packet()
397 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); in dce4_set_mute()
421 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_hdmi_enable()
459 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, in evergreen_dp_enable()
H A Devergreen.c1753 WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY); in evergreen_hpd_set_polarity()
4645 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in evergreen_irq_ack()
4650 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in evergreen_irq_ack()
4655 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_ack()
H A Dsi.c6160 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); in si_irq_ack()
6165 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); in si_irq_ack()
H A Dradeon.h2544 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v3_0.c563 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); in vce_v3_0_mc_resume()
H A Ddce_v8_0.c1675 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, in dce_v8_0_afmt_setmode()
1683 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c721 WREG32_OR(reg, asid); in goya_mmu_prepare_reg()
1472 WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset, in _goya_tpc_mbist_workaround()
1487 WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset, in _goya_tpc_mbist_workaround()
/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h2604 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) macro
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c5970 WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT)); in gaudi_debugfs_read_dma()
6048 WREG32_OR(reg, asid); in gaudi_mmu_prepare_reg()