| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v3_0_3.c | 184 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_3_init_system_aperture_regs()
392 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
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| H A D | gfxhub_v11_5_0.c | 183 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v11_5_0_init_system_aperture_regs()
402 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v11_5_0_gart_disable()
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| H A D | gfxhub_v3_0.c | 179 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_init_system_aperture_regs()
399 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
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| H A D | gfxhub_v12_0.c | 187 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v12_0_init_system_aperture_regs()
407 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v12_0_gart_disable()
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| H A D | gfx_v9_4_3.c | 356 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, in gfx_v9_4_3_init_golden_registers()
359 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, in gfx_v9_4_3_init_golden_registers()
1354 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_4_3_xcc_enable_save_restore_machine()
1502 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1519 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1522 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1538 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
1945 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_kiq_init_register()
2046 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v9_4_3_xcc_kiq_init_register()
2335 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_fini()
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| H A D | soc15_common.h | 58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ macro
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| H A D | nbif_v6_3_1.c | 158 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbif_v6_3_1_enable_doorbell_aperture()
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| H A D | nbio_v4_3.c | 155 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v4_3_enable_doorbell_aperture()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 501 WREG32_FIELD15_PREREG(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v11()
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| H A D | gfx_v12_0.c | 1689 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v12_0_constants_init()
1805 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v12_0_rlc_reset()
1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v12_0_rlc_reset()
1840 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_0_rlc_start()
3148 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v12_0_kiq_init_register()
3242 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v12_0_kiq_init_register()
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| H A D | gfx_v11_0.c | 2001 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
2129 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2131 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2164 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
4241 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4335 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
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