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Searched refs:WREG32_FIELD15 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c141 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in hdp_v4_0_init_registers()
151 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in hdp_v4_0_init_registers()
154 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); in hdp_v4_0_init_registers()
H A Ddf_v1_7.c117 WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0, in df_v1_7_enable_ecc_force_par_wr_rmw()
H A Dgfxhub_v2_0.c181 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_0_init_system_aperture_regs()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
H A Dsoc15_common.h50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ macro
H A Damdgpu_amdkfd_gfx_v10_3.c513 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v10_3()
H A Dgmc_v9_0.c2174 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v9_0_hw_init()
2176 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v9_0_hw_init()
H A Damdgpu_amdkfd_gfx_v10.c534 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()