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Searched refs:WREG32_FIELD (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v3_0.c165 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); in vce_v3_0_override_vce_clock_gating()
249 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_firmware_loaded()
251 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_firmware_loaded()
303 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); in vce_v3_0_start()
308 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v3_0_start()
310 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_start()
316 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); in vce_v3_0_start()
345 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); in vce_v3_0_stop()
348 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_stop()
602 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v3_0_mc_resume()
[all …]
H A Dvce_v2_0.c206 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v2_0_mc_resume()
262 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v2_0_start()
263 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v2_0_start()
265 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v2_0_start()
552 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); in vce_v2_0_soft_reset()
H A Dgfx_v6_0.c2478 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2547 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2549 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2822 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2823 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); in gfx_v6_0_enable_gfx_cgpg()
2825 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2875 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()
H A Damdgpu_amdkfd_gfx_v8.c408 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
H A Duvd_v3_1.c211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
H A Damdgpu.h1361 #define WREG32_FIELD(reg, field, val) \ macro
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1798 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset, in goya_init_golden_registers()
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c2530 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset, in gaudi_init_golden_registers()