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Searched refs:WM_SOCCLK (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h39 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h64 WM_SOCCLK = 0, enumerator
H A Dsmu9_driver_if.h342 WM_SOCCLK = 0, enumerator
H A Dsmu11_driver_if.h693 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c476 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn31_build_watermark_ranges()
477 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
478 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
479 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges()
480 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn31_build_watermark_ranges()
H A Ddcn31_smu.h67 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h66 WM_SOCCLK = 0, enumerator
H A Dsmu13_driver_if_yellow_carp.h65 WM_SOCCLK = 0, enumerator
H A Dsmu12_driver_if.h66 WM_SOCCLK = 0, enumerator
H A Dsmu13_driver_if_v13_0_4.h66 WM_SOCCLK = 0, enumerator
H A Dsmu11_driver_if_vangogh.h65 WM_SOCCLK = 0, enumerator
H A Dsmu15_driver_if_v15_0_0.h61 WM_SOCCLK = 0, enumerator
H A Dsmu11_driver_if_navi10.h1037 WM_SOCCLK = 0, enumerator
H A Dsmu11_driver_if_sienna_cichlid.h1635 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h56 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c442 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
444 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
446 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
448 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
451 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c698 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
700 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
702 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
704 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
707 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c533 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
535 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
537 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
539 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
542 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h55 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h70 WM_SOCCLK = 0, enumerator
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c547 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn314_build_watermark_ranges()
548 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
549 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
550 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn314_build_watermark_ranges()
551 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn314_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h64 WM_SOCCLK = 0, enumerator
H A Ddcn35_clk_mgr.c933 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn35_build_watermark_ranges()
934 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
935 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
936 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn35_build_watermark_ranges()
937 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn35_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c682 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v15_0_0_set_watermarks_table()
684 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v15_0_0_set_watermarks_table()
686 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v15_0_0_set_watermarks_table()
688 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v15_0_0_set_watermarks_table()
691 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v15_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h586 WM_SOCCLK = 0, enumerator