Searched refs:VT1724_SPDIF_MASTER (Results 1 – 2 of 2) sorted by relevance
130 #define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ macro
508 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); in juli_set_rate()