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Searched refs:VM_L2_PROTECTION_FAULT_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c382 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
386 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
388 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
391 VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
396 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
402 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_0_set_fault_enable_default()
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H A Dgfxhub_v1_2.c495 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
497 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
499 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
501 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
504 VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
507 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
509 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
511 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
513 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
515 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in gfxhub_v1_2_xcc_set_fault_enable_default()
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H A Dmmhub_v1_0.c433 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
435 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
437 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
439 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
442 VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
445 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
447 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
449 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
451 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
453 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, in mmhub_v1_0_set_fault_enable_default()
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H A Dgfxhub_v2_1.c556 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_save_regs()
591 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_restore_regs()
H A Damdgpu_gmc.h342 u64 VM_L2_PROTECTION_FAULT_CNTL; member