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Searched refs:VIASR (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/video/fbdev/via/
H A Dviamode.c11 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
12 {VIASR, SR15, 0x02, 0x02},
13 {VIASR, SR16, 0xBF, 0x08},
14 {VIASR, SR17, 0xFF, 0x1F},
15 {VIASR, SR18, 0xFF, 0x4E},
16 {VIASR, SR1A, 0xFB, 0x08},
17 {VIASR, SR1E, 0x0F, 0x01},
18 {VIASR, SR2A, 0xFF, 0x00},
44 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
45 {VIASR, SR15, 0x02, 0x02},
[all …]
H A Dvia_clock.c44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
45 via_write_reg(VIASR, 0x46, data & 0xFF); in cle266_set_primary_pll_encoded()
46 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF); in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
53 via_write_reg(VIASR, 0x44, data & 0xFF); in k800_set_primary_pll_encoded()
54 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); in k800_set_primary_pll_encoded()
55 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF); in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
61 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ in cle266_set_secondary_pll_encoded()
[all …]
H A Ddvi.c44 sr2a = viafb_read_reg(VIASR, SR2A); in viafb_tmds_trasmitter_identify()
45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
51 sr2a = viafb_read_reg(VIASR, SR2A); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
54 sr1e = viafb_read_reg(VIASR, SR1E); in viafb_tmds_trasmitter_identify()
55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
60 sr1e = viafb_read_reg(VIASR, SR1E); in viafb_tmds_trasmitter_identify()
61 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
65 sr3e = viafb_read_reg(VIASR, SR3E); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
[all …]
H A Dvia-gpio.c31 .vg_io_port = VIASR,
37 .vg_io_port = VIASR,
43 .vg_io_port = VIASR,
49 .vg_io_port = VIASR,
55 .vg_io_port = VIASR,
61 .vg_io_port = VIASR,
94 reg = via_read_reg(VIASR, gpio->vg_port_index); in via_gpio_set()
100 via_write_reg(VIASR, gpio->vg_port_index, reg); in via_gpio_set()
123 via_write_reg_mask(VIASR, gpio->vg_port_index, 0, in via_gpio_dir_input()
138 reg = via_read_reg(VIASR, gpio->vg_port_index); in via_gpio_get()
[all …]
H A Dvia_utility.c138 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_set_gamma_table()
151 sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A); in viafb_set_gamma_table()
152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
180 viafb_write_reg(SR1A, VIASR, sr1a); in viafb_set_gamma_table()
193 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_get_gamma_table()
206 sr1a = viafb_read_reg(VIASR, SR1A); in viafb_get_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
219 viafb_write_reg(SR1A, VIASR, sr1a); in viafb_get_gamma_table()
H A Dhw.c668 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); in viafb_set_primary_color_register()
674 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); in viafb_set_secondary_color_register()
713 via_write_reg_mask(VIASR, 0x16, value, 0x40); in set_crt_source()
803 via_write_reg_mask(VIASR, 0x1E, value, 0xC0); in set_dvp0_state()
821 via_write_reg_mask(VIASR, 0x1E, value, 0x30); in set_dvp1_state()
839 via_write_reg_mask(VIASR, 0x2A, value, 0x03); in set_lvds1_state()
857 via_write_reg_mask(VIASR, 0x2A, value, 0x0C); in set_lvds2_state()
960 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
995 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); in viafb_load_reg()
1024 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); in viafb_load_fetch_count_reg()
[all …]
H A Dvia-core.c27 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
28 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
29 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
30 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c },
31 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
40 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
41 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
42 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
43 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x2c },
44 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
H A Dviafbdev.c1114 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 | in viafb_dvp0_proc_show()
1115 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1; in viafb_dvp0_proc_show()
1117 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 | in viafb_dvp0_proc_show()
1118 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2; in viafb_dvp0_proc_show()
1155 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1157 viafb_write_reg_mask(SR1B, VIASR, in viafb_dvp0_proc_write()
1161 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1163 viafb_write_reg_mask(SR1E, VIASR, in viafb_dvp0_proc_write()
1188 dvp1_data_dri = (viafb_read_reg(VIASR, SR65) & 0x0c) >> 2; in viafb_dvp1_proc_show()
1189 dvp1_clk_dri = viafb_read_reg(VIASR, SR65) & 0x03; in viafb_dvp1_proc_show()
[all …]
H A Dlcd.c704 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30); in viafb_lcd_disable()
725 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20); in viafb_lcd_disable()
769 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30); in viafb_lcd_enable()
791 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20); in viafb_lcd_enable()
H A Dvia_modesetting.c187 via_write_reg_mask(VIASR, 0x15, value, 0x1C); in via_set_primary_color_depth()
/linux/include/linux/
H A Dvia-core.h184 #define VIASR 0x3C4 macro