Searched refs:VCO_REF_CLK_RATE (Results 1 – 5 of 5) sorted by relevance
34 #define VCO_REF_CLK_RATE 19200000 macro149 rem = rate % VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_set_rate()153 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()154 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()158 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()159 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()248 u32 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_recalc_rate()256 ref_clk += (doubler * VCO_REF_CLK_RATE); in dsi_pll_28nm_clk_recalc_rate()
37 #define VCO_REF_CLK_RATE 19200000 macro172 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); in pll_14nm_ssc_calc()175 period = (u32)VCO_REF_CLK_RATE / 1000; in pll_14nm_ssc_calc()184 ref = VCO_REF_CLK_RATE; in pll_14nm_ssc_calc()211 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_dec_frac_calc()254 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_calc_vco_count()545 if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) in dsi_pll_14nm_vco_prepare()546 dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); in dsi_pll_14nm_vco_prepare()
39 #define VCO_REF_CLK_RATE 19200000 macro116 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac()161 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()412 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_10nm_vco_recalc_rate()517 VCO_REF_CLK_RATE); in dsi_10nm_pll_restore_state()
39 #define VCO_REF_CLK_RATE 19200000 macro 112 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac() 178 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc() 482 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_7nm_vco_recalc_rate() 587 VCO_REF_CLK_RATE); in dsi_7nm_pll_restore_state()
42 #define VCO_REF_CLK_RATE 27000000 macro103 val = VCO_REF_CLK_RATE / 10; in dsi_pll_28nm_clk_set_rate()