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Searched refs:VCLK_SRC_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drv770.c66 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
132 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
H A Drv770d.h58 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
H A Devergreend.h363 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
H A Dr600d.h1577 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
H A Dr600.c211 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
289 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
H A Devergreen.c1198 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
1271 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
/linux/include/video/
H A Dradeon.h920 #define VCLK_SRC_SEL_MASK 0x03 macro
/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1378 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()
1438 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()