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Searched refs:VC4_SET_FIELD (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_phy.c441 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT)); in vc5_hdmi_phy_init()
446 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT)); in vc5_hdmi_phy_init()
449 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
454 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO)); in vc5_hdmi_phy_init()
457 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) | in vc5_hdmi_phy_init()
458 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD)); in vc5_hdmi_phy_init()
464 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL)); in vc5_hdmi_phy_init()
469 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) | in vc5_hdmi_phy_init()
470 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) | in vc5_hdmi_phy_init()
471 VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP)); in vc5_hdmi_phy_init()
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H A Dvc4_dpi.c160 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT); in vc4_dpi_encoder_enable()
170 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
174 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
176 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, in vc4_dpi_encoder_enable()
180 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
183 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
187 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
190 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
194 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, in vc4_dpi_encoder_enable()
198 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2, in vc4_dpi_encoder_enable()
H A Dvc4_hvs.c650 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
652 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
657 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
659 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
709 VC4_SET_FIELD(mode->hdisplay - 1, in vc6_hvs_init_channel()
712 VC4_SET_FIELD(mode->vdisplay - 1, in vc6_hvs_init_channel()
848 VC4_SET_FIELD(vc4_state->mm.start, in vc4_hvs_install_dlist()
1316 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); in vc4_hvs_hw_init()
1321 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); in vc4_hvs_hw_init()
1326 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); in vc4_hvs_hw_init()
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H A Dvc4_txp.c319 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
322 ctrl |= VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE); in vc4_txp_connector_atomic_commit()
354 VC4_SET_FIELD(hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
355 VC4_SET_FIELD(vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
H A Dvc4_validate.c432 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
434 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
H A Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro