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Searched refs:UVD_VCPU_CNTL__CLK_EN_MASK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c895 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_5_start_dpg_mode()
942 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_5_start_dpg_mode()
1029 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v4_0_5_start()
1260 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v4_0_5_stop()
H A Dvcn_v2_5.c888 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
951 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
1046 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_5_start()
1475 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_5_stop()
H A Dvcn_v3_0.c1008 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1069 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1168 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v3_0_start()
1615 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v3_0_stop()
H A Dvcn_v2_0.c859 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_0_start_dpg_mode()
997 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_0_start()
1213 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_0_stop()
H A Dvcn_v1_0.c894 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
1025 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v1_0_start_dpg_mode()
1183 ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_stop_spg_mode()
H A Duvd_v7_0.c904 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_sriov_start()
1035 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h665 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Duvd_3_1_sh_mask.h543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_4_2_sh_mask.h547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_4_0_sh_mask.h766 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Duvd_5_0_sh_mask.h579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_6_0_sh_mask.h581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1187 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_2_5_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_2_6_0_sh_mask.h112 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3818 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3767 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3933 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4066 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4104 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro