Home
last modified time | relevance | path

Searched refs:UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h656 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Duvd_3_1_sh_mask.h525 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff macro
H A Duvd_4_2_sh_mask.h529 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff macro
H A Duvd_4_0_sh_mask.h754 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL macro
H A Duvd_5_0_sh_mask.h561 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff macro
H A Duvd_6_0_sh_mask.h563 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1176 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_2_5_sh_mask.h2686 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2682 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_2_6_0_sh_mask.h39 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3744 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3688 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3856 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3990 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4025 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK … macro