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Searched refs:UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h650 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Duvd_3_1_sh_mask.h521 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff macro
H A Duvd_4_2_sh_mask.h525 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff macro
H A Duvd_4_0_sh_mask.h752 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL macro
H A Duvd_5_0_sh_mask.h557 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff macro
H A Duvd_6_0_sh_mask.h559 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1170 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_2_5_sh_mask.h2680 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2676 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_2_6_0_sh_mask.h33 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3738 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3682 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3850 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3984 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4019 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK … macro