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Searched refs:UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h652 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Duvd_3_1_sh_mask.h524 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h528 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h749 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000 macro
H A Duvd_5_0_sh_mask.h560 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h562 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1172 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2682 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2678 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h35 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3740 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h3684 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h3852 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3986 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4021 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT … macro