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Searched refs:UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h646 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Duvd_3_1_sh_mask.h520 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h524 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h747 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000 macro
H A Duvd_5_0_sh_mask.h556 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h558 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1166 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2676 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2672 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h29 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3734 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h3678 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h3846 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3980 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4015 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT … macro